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  user?s manual v850es/pm1 32-bit single-chip microcontroller hardware document no. u16237ej3v0ud00 (3rd edition) date published january 2006 n cp(k) printed in japan ? pd703228 2003
user?s manual u16237ej3v0ud 2 [memo]
user?s manual u16237ej3v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
user?s manual u16237ej3v0ud 4 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of july, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
user?s manual u16237ej3v0ud 5 preface readers this manual is intended for users who wish to understand the functions of the v850es/pm1 ( pd703228) and design application systems using this product. purpose this manual is intended to give users an understanding of the har dware functions of the v850es/pm1 shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture ( v850es architecture user?s manual ). hardware architecture ? pin functions ? data types ? cpu function ? register set ? on-chip peripheral functions ? instruction format and instruction set ? electrical specifications ? interrupts and exceptions ? pipeline operation how to read this manual it is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to find the details of a regi ster where the name is known see appendix a register index . to understand the details of an instruction function refer to the v850es architecture user?s manual available separately. register format the name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defi ned as a reserved word in the device file. to understand the overall func tions of the v850es/pm1 read this manual according to the contents . to know the electrical spec ifications of the v850es/pm1 see chapter 20 electrical specifications . the mark shows major revised poi nts. the revised points can be easily searched by copying an ?? in the pdf file and specifying it in the ?find what:? field.
user?s manual u16237ej3v0ud 6 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresse s on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 ( address space, memory capacity): k (kilo): 2 10 = 1024 m (mega): 2 20 = 1024 2 g (giga): 2 30 = 1024 3 related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850es/pm1 document name document no. v850es architecture user?s manual u15943e v850es/pm1 hardware user?s manual this manual documents related to development tools document name document no. ie-v850es-g1 (in-circuit emulator) u16313e ie-703228-g1-em1 (in-circuit em ulator option board) u16879e operation u17293e c language u17291e assembly language u17292e ca850 ver. 3.00 c compiler package link directives u17294e pm+ ver. 6.00 project manager u17178e id850 ver. 3.00 integrated debugger operation u17358e tw850 (ver. 2.00) (performance analysis tuning tool) u17241e sm850 ver. 2.50 system simulator operation u16218e operation u17246e sm+ system simulator user open interface u17247e sm850 ver. 2.00 or later system si mulator external part user open interface specifications u14873e basics u13430e installation u13410e rx850 ver. 3.13 or later real-time os technical u13431e basics u13773e installation u13774e rx850 pro ver. 3.13 real-time os technical u13772e rd850 ver. 3.01 task debugger u13737e rd850 pro ver. 3.01 task debugger u13916e az850 ver. 3.20 system performance analyzer u14410e
user?s manual u16237ej3v0ud 7 contents chapter 1 introduction ...................................................................................................... ...........13 1.1 overview....................................................................................................................... .............13 1.2 features....................................................................................................................... ..............14 1.3 application fields ............................................................................................................. .......15 1.4 ordering information ........................................................................................................... ....15 1.5 pin configuration (top view) ....................................... ...........................................................1 6 1.6 function block configuration......................................... ........................................................18 1.6.1 internal bl ock di agram ......................................................................................................... ........ 18 1.6.2 internal units................................................................................................................. ............... 19 chapter 2 pin funct ions.................................................................................................... ............21 2.1 pin function list .............................................................................................................. ........21 2.2 pin status ..................................................................................................................... .............27 2.3 types of pin i/o circuits, i/o buffer power supplies, and connection of unused pins ..28 chapter 3 cpu function..................................................................................................... ............31 3.1 features....................................................................................................................... ..............31 3.2 cpu register set............................................................................................................... .......32 3.2.1 program regi ster set........................................................................................................... ......... 33 3.2.2 system regi ster set ............................................................................................................ ......... 34 3.3 operation modes ................................................................................................................ ......40 3.3.1 operati on m odes ................................................................................................................ ......... 40 3.3.2 specifying oper ation mode...................................................................................................... .... 40 3.4 address space .................................................................................................................. .......41 3.4.1 cpu address space .............................................................................................................. ...... 41 3.4.2 wrap-around of cpu address s pace........................................................................................... 42 3.4.3 memory map ..................................................................................................................... .......... 43 3.4.4 areas.......................................................................................................................... ................. 45 3.4.5 recommended use of address s pace ......................................................................................... 47 3.4.6 peripheral i/o regist ers ....................................................................................................... ........ 49 3.4.7 special r egister s.............................................................................................................. ............ 55 3.4.8 cauti ons ....................................................................................................................... ............... 59 chapter 4 port f unctions................................................................................................... .........63 4.1 features....................................................................................................................... ..............63 4.2 basic configuration of port......................................... ........................................................... .63 4.3 port configuration......................................................... .................................................... .......64 4.3.1 port 0 ......................................................................................................................... ................. 68 4.3.2 port 1 ......................................................................................................................... ................. 71 4.3.3 port 2 ......................................................................................................................... ................. 74 4.3.4 port 3 ......................................................................................................................... ................. 76 4.3.5 port 4 ......................................................................................................................... ................. 79
user?s manual u16237ej3v0ud 8 4.3.6 port 9......................................................................................................................... ..................82 4.3.7 port cm ........................................................................................................................ ...............87 4.3.8 port cs........................................................................................................................ ................89 4.3.9 port ct ........................................................................................................................ ................91 4.3.10 port dh........................................................................................................................ ................93 4.3.11 port dl ........................................................................................................................ ................95 4.4 block diagram.................................................................................................................. .........98 4.5 register settings for ports when alternate func tion is used ......................................... 113 4.6 cautions ....................................................................................................................... .......... 119 4.6.1 cautions on bit manipulation instru ction for port n r egister (pn) ................................................119 chapter 5 bus control function ................................ .......................................................... 12 0 5.1 features....................................................................................................................... ........... 120 5.2 bus control pins............................................................................................................... ..... 121 5.2.1 pin status when internal rom, internal ra m, or on-chip peripher al i/o is a ccessed ................121 5.2.2 pin status in eac h operation mode ............................................................................................12 1 5.3 memory block function........................................................................................................ 12 2 5.3.1 chip select c ontrol f unction ................................................................................................... ....123 5.4 bus access ..................................................................................................................... ....... 124 5.4.1 number of clo cks for a ccess .................................................................................................... .124 5.4.2 bus size setti ng func tion...................................................................................................... ......124 5.4.3 access by bus si ze ............................................................................................................. .......125 5.5 wait function .................................................................................................................. ....... 132 5.5.1 programmable wa it func tion ..................................................................................................... .132 5.5.2 external wait func tion ......................................................................................................... .......133 5.5.3 relationship between programmabl e wait and exte rnal wa it ..................................................... 133 5.5.4 programmable address wait func tion ........................................................................................134 5.6 idle state insertion function ............................................ .................................................... 13 5 5.7 bus priority ................................................................................................................... ......... 136 5.8 bus timing ..................................................................................................................... ........ 137 chapter 6 clock generation function .................... .......................................................... 140 6.1 overview....................................................................................................................... .......... 140 6.2 configuration .................................................................................................................. ....... 141 6.3 register ....................................................................................................................... ........... 143 6.4 operation...................................................................................................................... .......... 146 6.4.1 operation of each cl ock........................................................................................................ .....146 6.4.2 clock output functi on .......................................................................................................... .......146 6.4.3 external clock input f unction.................................................................................................. ....146 chapter 7 16-bit timer/event counters 00 to 03 ........................................................... 147 7.1 functions...................................................................................................................... .......... 147 7.2 configuration .................................................................................................................. ....... 148 7.3 registers ...................................................................................................................... .......... 153 7.4 operation...................................................................................................................... .......... 160 7.4.1 interval time r operat ion....................................................................................................... .......160 7.4.2 square wave out put operat ion................................................................................................... 163
user?s manual u16237ej3v0ud 9 7.4.3 external event c ounter operat ion .............................................................................................. 1 66 7.4.4 operation in clear & start mode ent ered by ti0n0 pin valid edge input ..................................... 169 7.4.5 free-running time r operat ion................................................................................................... .. 185 7.4.6 ppg output operatio n........................................................................................................... ..... 194 7.4.7 one-shot pulse out put operat ion ............................................................................................... 1 97 7.4.8 pulse width measur ement operat ion ......................................................................................... 202 7.5 special use of tm0n ............................................................................................................ ..210 7.5.1 rewriting cr0n1 register during tm0n oper ation ..................................................................... 210 7.5.2 setting lvs0n and lvr0n bi ts.................................................................................................. 2 10 7.6 cautions ....................................................................................................................... ...........212 chapter 8 16-bit timer/event counters 10 and 11 .........................................................216 8.1 features....................................................................................................................... ............216 8.2 function overview .............................................................................................................. ...216 8.3 configuration .................................................................................................................. ........217 8.4 registers ...................................................................................................................... ...........222 8.5 operation...................................................................................................................... ...........227 8.6 application examples ........................................................................................................... .234 8.7 cautions ....................................................................................................................... ...........243 chapter 9 8-bit timer/event counters 20 and 21 ...........................................................244 9.1 function overview .............................................................................................................. ...244 9.2 configuration .................................................................................................................. ........245 9.3 registers ...................................................................................................................... ...........248 9.4 operation...................................................................................................................... ...........251 9.4.1 operation as interval timer (8 bits) ........................................................................................... . 251 9.4.2 operation as external ev ent counter (8 bits ) ............................................................................. 253 9.4.3 square-wave output operati on (8-bit re soluti on)........................................................................ 254 9.4.4 8-bit pwm output operat ion..................................................................................................... .. 256 9.4.5 operation as interval timer ( 16 bits ) .......................................................................................... 259 9.4.6 operation as external ev ent counter ( 16 bits ) ........................................................................... 261 9.4.7 square-wave output operati on (16-bit re soluti on)...................................................................... 262 9.5 cautions ....................................................................................................................... ...........263 chapter 10 real-time counter function.............. ...............................................................264 10.1 functions ...................................................................................................................... ..........264 10.2 configuration .................................................................................................................. ........264 10.3 registers ...................................................................................................................... ...........265 10.4 operation...................................................................................................................... ...........271 10.4.1 initializing count er and c ount-up.............................................................................................. .. 271 10.4.2 rewriting count er .............................................................................................................. ........ 271 10.4.3 controlling interrupt request signal output ................................................................................. 271 10.4.4 cauti ons ....................................................................................................................... ............. 272 chapter 11 watchdog timer func tions...............................................................................273 11.1 functions ...................................................................................................................... ..........273 11.2 configuration .................................................................................................................. ........274
user?s manual u16237ej3v0ud 10 11.3 registers ...................................................................................................................... .......... 275 11.4 operation...................................................................................................................... .......... 277 11.4.1 operation as watchdog ti mer.................................................................................................... .277 11.4.2 operation as in terval timer .................................................................................................... ....278 11.4.3 monitoring reset by wa tchdog timer (wdt) ...............................................................................279 chapter 12 a/d converter ................................................................................................... ...... 280 12.1 functions...................................................................................................................... .......... 280 12.2 configuration .................................................................................................................. ....... 281 12.3 registers ...................................................................................................................... .......... 284 12.4 operation...................................................................................................................... .......... 286 12.5 cautions ....................................................................................................................... .......... 288 chapter 13 pwm function.................................................................................................... ....... 289 13.1 features....................................................................................................................... ........... 289 13.2 configuration .................................................................................................................. ....... 289 13.3 registers ...................................................................................................................... .......... 290 13.4 operation...................................................................................................................... .......... 292 13.4.1 basic oper ation................................................................................................................ ..........292 13.4.2 repeat fr equency ............................................................................................................... .......294 13.5 cautions ....................................................................................................................... .......... 295 chapter 14 asynchronous serial interface n (uartn) .............................................. 296 14.1 features....................................................................................................................... ........... 296 14.2 configuration .................................................................................................................. ....... 297 14.3 registers ...................................................................................................................... .......... 299 14.4 interrupt requests............................................................................................................. .... 306 14.5 operation...................................................................................................................... .......... 307 14.6 dedicated baud rate generator n (brgn) .................... ..................................................... 319 14.7 cautions ....................................................................................................................... .......... 326 chapter 15 clocked serial interface n (csin) ............................................................... 327 15.1 features....................................................................................................................... ........... 327 15.2 configuration .................................................................................................................. ....... 327 15.3 registers ...................................................................................................................... .......... 329 15.4 operation...................................................................................................................... .......... 333 15.5 output pins .................................................................................................................... ........ 336 15.6 system configuration example ........................................................................................... 337 chapter 16 interrupt/exception processing fu nction............................................... 338 16.1 features....................................................................................................................... ........... 338 16.2 non-maskable interrupts ...................................................................................................... 34 1 16.2.1 operat ion...................................................................................................................... .............342 16.2.2 restore........................................................................................................................ ..............343 16.2.3 np fl ag........................................................................................................................ ...............344 16.3 maskable interrupts............................................................................................................ ... 345 16.3.1 operat ion...................................................................................................................... .............345
user?s manual u16237ej3v0ud 11 16.3.2 restor e........................................................................................................................ .............. 347 16.3.3 priorities of ma skable inte rrupts .............................................................................................. .. 348 16.3.4 interrupt control r egister ( xxicn)............................................................................................. ... 352 16.3.5 interrupt mask registers 0, 1 (imr0, imr1 ) ............................................................................... 354 16.3.6 in-service priority register (ispr) ............................................................................................ .. 355 16.3.7 id flag........................................................................................................................ ................ 356 16.4 external interrupt request input pins (nmi, in tp0 to intp2).............................................357 16.4.1 noise eliminat ion ...................................................................................................... ................... 357 16.4.2 edge detecti on ......................................................................................................... ................... 357 16.5 software exception ............................................................................................................. ...359 16.5.1 operat ion ...................................................................................................................... ............ 359 16.5.2 restor e........................................................................................................................ .............. 360 16.5.3 exception stat us flag (ep) ..................................................................................................... .... 361 16.6 exception trap ................................................................................................................. ......362 16.6.1 illegal opcode definit ion...................................................................................................... ....... 362 16.6.2 debug tr ap ..................................................................................................................... ........... 364 16.7 interrupt acknowledge time of cpu ....................................................................................366 16.8 periods in which interrupts are not acknowledged by cpu............................................367 chapter 17 standby function...................................... .......................................................... ...368 17.1 overview....................................................................................................................... ...........368 17.2 registers ...................................................................................................................... ...........371 17.3 halt mode...................................................................................................................... ........373 17.3.1 setting and operat ion st atus................................................................................................... ... 373 17.3.2 releasing ha lt m ode ............................................................................................................ .. 373 17.4 idle mode ...................................................................................................................... .........375 17.4.1 setting and operat ion st atus................................................................................................... ... 375 17.4.2 releasing id le m ode ............................................................................................................ ... 375 17.5 software stop mode ............................................................................................................. 377 17.5.1 setting and operat ion st atus................................................................................................... ... 377 17.5.2 releasing softwar e stop mode ............................................................................................... 377 17.6 securing oscillation stabilization time..................... ..........................................................379 17.7 subclock operation mode .....................................................................................................380 17.7.1 setting and operat ion st atus................................................................................................... ... 380 17.7.2 releasing subclock operation mode .......................................................................................... 380 17.7.3 registers to which access is dis abled in subclock operation mode ........................................... 381 17.8 sub-idle mode .................................................................................................................. .....382 17.8.1 setting and operat ion st atus................................................................................................... ... 382 17.8.2 releasing sub- idle mode ........................................................................................................ 382 17.9 sub-software stop mode .....................................................................................................384 17.9.1 setting and operat ion st atus................................................................................................... ... 384 17.9.2 releasing sub-softw are stop mode ........................................................................................ 384 chapter 18 reset function .................................................................................................. ......386 18.1 overview....................................................................................................................... ...........386 18.2 configuration .................................................................................................................. ........386 18.3 register ....................................................................................................................... ............387 18.4 operation...................................................................................................................... ...........388
user?s manual u16237ej3v0ud 12 chapter 19 rom correction function....................... .......................................................... 391 19.1 overview....................................................................................................................... .......... 391 19.2 registers ...................................................................................................................... .......... 392 19.2.1 correction address registers 0 to 3 (corad0 to corad3 ) .....................................................392 19.2.2 correction control r egister (c orcn) .........................................................................................393 19.3 rom correction operation and program flow .......... ........................................................ 393 chapter 20 electrical specifications ....................... .......................................................... 395 chapter 21 package drawing ................................................................................................. . 424 chapter 22 recommended soldering conditions... ........................................................ 425 appendix a register index .................................................................................................. ....... 426 appendix b instruction set list ........................................................................................... .. 432 b.1 conventions .................................................................................................................... ....... 432 b.2 instruction set (in alphabetical order) ....................... ........................................................ 435 appendix c revision history ................................................................................................. ..... 442 c.1 major revisions in this edition ........................................................................................... 442 c.2 revision history of preceding editions ......................... ..................................................... 443
user?s manual u16237ej3v0ud 13 chapter 1 introduction the v850es/pm1 is an nec electronics v850 series si ngle-chip microcontroller for real-time control. 1.1 overview the v850es/pm1 is a 32-bit single-chip microcontrolle r that employs the v850es cpu core and integrates peripheral functions such as rom/ram, timers/counter s, serial interfaces, an a/d converter, and pwm. the v850es core is used as the cpu with peripheral functions, such as a ? a/d converter, added. the v850es/pm1 features instructions ideal for digital servo control applications, such as multiplication instructions using a hardware multiplier, saturated operation instructio ns, and bit manipulation instructions, as well as basic instructions with a short real-time response speed and a 1-clock pitch. high-accuracy power measurement can be realized at a low cost by using the high-accuracy, 6-channel ? a/d converter, making the v850es/pm1 suitable for applications such as power meters and other measuring instruments.
chapter 1 introduction user?s manual u16237ej3v0ud 14 1.2 features minimum instruction execution time: 50 ns (main clock (f x ) = 20 mhz) 100 ns (main clock (f x ) = 10 mhz) 30.5 s (subclock (f xt ) = 32.768 khz) general-purpose registers: 32 bits 32 registers cpu features: signed multiplication (16 16 32): 1 to 2 clocks signed multiplication (32 32 64): 1 to 5 clocks saturated operation (with overflow/underflow detection function) 32-bit shift instruction: 1 clock bit manipulation instruction load/store instruction with long/short format memory space: 64 mb linear address space (for program/data) external expansion: up to 8 mb (of which 1 mb is used as internal rom space) memory block division function: 2, 2, 4 mb (total: 3 blocks) programmable wait function idle state insertion function ? internal memory: ram: 10 kb mask rom: 128 kb ? external bus interface: separate bus output 8/16-bit data bus sizing function 3-space chip select function wait functions ? programmable wait function ? external wait function idle state function interrupts/exceptions: non-maskable interrupt: 1 source maskable interrupts: 31 sources software exception: 32 sources exception trap: 1 source i/o lines: total: 68 (i/o ports) timer function: 16-bit timer/ev ent counter: 6 ch (pwm output) 8-bit timer/event counter: 2 ch (connectable in cascade) real-time counter (for watch): subclock/main clock operation: 1 ch counter for weeks, days, hours, minutes, and seconds, up to 4095 weeks. watchdog timer: 1 ch pwm (pulse width modulation): 4 ch serial interface: asynchronous serial interface (uart) clocked serial interface (csi) uart: 2 ch csi: 2 ch a/d converter: 16-bit resolution: 6 ch (12 inputs) rom correction: 4 places specifiable clock generator: main clock/subclock operation cpu clock: 5 steps (f xx , f xx /2, f xx /4, f xx /8, f xt ) power save function: halt/idle/stop/sub-idle/sub-stop mode package: 100-pin plastic lqfp (fine pitch) (14 14)
chapter 1 introduction user?s manual u16237ej3v0ud 15 1.3 application fields power meters, measuring instruments 1.4 ordering information part number package internal rom pd703228gc-003-8eu 100-pin plastic lqfp (fine pitch) (14 14) romless mode pd703228gc-004-8eu-a 100-pin plastic lqfp (fine pitch) (14 14) romless mode pd703228gc-xxx-8eu 100-pin plastic lqfp (fine pitch) (14 14) mask rom (128 kb) pd703228gc-xxx-8eu-a 100-pin plastic lqfp (fine pitch) (14 14) mask rom (128 kb) remarks 1. indicates rom code suffix. to use in the romless mode, specify code 003 or 004 when placing your order. 2. products with -a at the end of the part number are lead-free products.
chapter 1 introduction user?s manual u16237ej3v0ud 16 1.5 pin configuration (top view) v850es/pm1 100-pin plastic lqfp (fine pitch) (14 14) ? pd703228gc- -8eu p46/intp111/to11 p45/intp101/to10 p44/txd1 p43/rxd1 p42/sck0 p41/so0 p40/si0 pcs2/cs2 pcs1/cs1 pcs0/cs0 ev dd ev ss pdl15/d15 pdl14/d14 pdl13/d13 pdl12/d12 pdl11/d11 pdl10/d10 pdl9/d9 pdl8/d8 pdl7/d7 pdl6/d6 pdl5/d5 pdl4/d4 pdl3/d3 p34/sck1 p33/so1 p32/si1 p31/txd0 p30/rxd0 p10/pwm0 p11/to00/pwm1 p12/to01/pwm2 p13/to20/pwm3 p14/to21/ti21 v dd v ss x1 x2 reset xt1 xt2 ev ss ev dd p90/a0 p91/a1 p92/a2 p93/a3 p94/a4 p95/a5 p96/a6 p97/a7 p98/a8/ti030 p99/a9/ti031 p910/a10/ti020 p911/a11/ti021 p912/a12/ti010 p913/a13/ti011 p914/a14/ti000 p915/a15/ti001 p20/to02 p21/to03 ev ss ev dd pcm1/clkout pcm0/wait pdh0/a16 pdh1/a17 pdh2/a18 pct0/wr0 pct1/wr1 pct4/rd pdl0/d0 pdl1/d1 pdl2/d2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p35/intp100/ti10/tclr10 p36/intp110/ti11/tclr11 ic1 note 1 av ss ic0 note 2 ani10 ani11 ani30 ani31 ani50 ani51 av refout av refin ani41 ani40 ani21 ani20 ani01 ani00 av dd mode p00/nmi p01/intp0 p02/intp1 p03/intp2/ti20 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 notes 1. connect this pin directly to v ss . 2. connect this pin directly to av ss .
chapter 1 introduction user?s manual u16237ej3v0ud 17 pin identification a0 to a18: ani00, ani01, ani10, ani11, ani20, ani21, ani30, ani31, ani40, ani41, ani50, ani51: av dd : av refin : av refout : av ss : clkout: cs0 to cs2: d0 to d15: ev dd : ev ss : ic0, ic1: intp0 to intp2: intp100, intp101, intp110, intp111: mode: nmi: p00 to p03: p10 to p14: p20, p21: p30 to p36: p40 to p46: p90 to p915: pcm0, pcm1: pcs0 to pcs2: address bus analog input analog v dd analog reference voltage input analog reference voltage output analog v ss clock output chip select data bus power supply for port ground for port internally connected external interrupt input timer input operation mode select non-maskable interrupt request port 0 port 1 port 2 port 3 port 4 port 9 port cm port cs pct0, pct1, pct4: pdh0 to pdh2: pdl0 to pdl15: pwm0 to pwm3: rd: reset: rxd0, rxd1: sck0, sck1: si0, si1: so0, so1: tclr10, tclr11: ti000, ti001, ti010, ti011, ti020, ti021, ti030, ti031, ti10, ti11, ti20, ti21: to00 to to03, to10, to11, to20, to21: txd0, txd1: v dd : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: port ct port dh port dl pulse width modulation read strobe reset receive data serial clock serial input serial output timer clear input timer input timer output transmit data power supply ground wait lower byte write strobe upper byte write strobe crystal for main clock crystal for subclock
chapter 1 introduction user?s manual u16237ej3v0ud 18 1.6 function block configuration 1.6.1 internal block diagram ? v850es/pm1 nmi intp100, intp101 intp110, intp111 to10, to11 ti10, ti11 tclr10, tclr11 so0, so1 si0, si1 sck0, sck1 intp0 to intp2 intc timer/counter (16-bit timer) 2 ch to00 to to03 ti000 to ti030 ti001 to ti031 timer/counter (16-bit timer) 4 ch to20, to21 ti20, ti21 timer/counter (8-bit timer) 2 ch txd0, txd1 rxd0, rxd1 uart 2 ch watchdog timer real-time counter ram mask rom 10 kb pc general-purpose registers 32 bits 32 multiplier (16 16 32) alu system registers 32-bit barrel shifter cpu cs0 to cs2 d0 to d15 a0 to a18 wr0, wr1 rd wait port cg rg a/d converter pcs0 to pcs2 pcm0, pcm1 pct0, pct1, pct4 pdh0 to pdh2 pdl0 to pdl15 p90 to p915 p40 to p46 p30 to p36 p20, p21 p10 to p14 p00 to p03 ani00 to ani51 av refin av refout av dd av ss clkout x1 x2 xt1 xt2 reset v dd , ev dd v ss , ev ss ic0, ic1 instruction queue bcu csi 2 ch rom correction 128 kb pwm0 to pwm3 pwm mode
chapter 1 introduction user?s manual u16237ej3v0ud 19 1.6.2 internal units (1) cpu the cpu can execute almost all instruction processing , such as address calculation, arithmetic logic operations, and data transfer, with 1 clock, using a 5-stage pipeline. the cpu has dedicated hardware units such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) to speed up complicated processing. (2) bus control unit (bcu) the bcu starts the required external bus cycles in a ccordance with the physical address obtained by the cpu. if the cpu does not request the start of a bus cycle when an instruction is fetched from the external memory area, the bcu generates a prefetch address and prefetch es an instruction code. the prefetched instruction code is loaded to the internal instruction queue. (3) rom this is 128 kb mask rom mapped to addresses 0 000000h to 001ffffh. the cpu can access the rom with 1 clock when an instruction is fetched. (4) ram this is 10 kb ram mapped to addresses 3ffc800h to 3ffefffh. it can be accessed by the cpu with 1 clock when data is accessed. (5) interrupt controller (intc) the intc processes hardware interrupt requests (nmi, in tp0 to intp2) from the internal peripheral hardware and external sources. eight levels of priority can be sp ecified for these interrupt requests. the intc can also control multiple interrupt servicing. (6) clock generator (cg) two oscillators, the main clock oscillator and subclock oscillator, are provided and generate the main clock oscillation frequency (f x ) and subclock frequency (f xt ). the cpu clock frequency (f cpu ) can be selected from five types of clocks, f xx , f xx /2, f xx /4, f xx /8, and f xt . (7) timer/counter a six-channel 16-bit timer/event counter is available, enabling pulse interval and frequency measurement and programmable pulse output. a two-channel 8-bit timer/event counter is also available and can be cascaded as a 16-bit timer. (8) real-time counter (for watch) this real-time counter counts the refer ence time from the subclock and can also be used as an interval timer. week, day, hour, minute, and second counters are provided, and up to 4095 weeks can be counted. (9) watchdog timer a watchdog timer that detects program han g-up and system errors is provided. this watchdog timer can also be used as an interval timer. when used as a watchdog timer, an internal reset request signal (wdtres) is generated if the watchdog timer overflows. when used as an interval timer, a maska ble interrupt request signal (intwdtm) is generated when the timer overflows.
chapter 1 introduction user?s manual u16237ej3v0ud 20 (10) pwm (pulse width modulation) four pwm signal output channels are available. the resolution is selectable from 8 to 10, or 12 bits. (11) serial interface the v850es/pm1 has asynchronous serial interfaces (uart0 and uart1) and clocked serial interfaces (csi0 and csi1) as the serial interfaces. the v850es/pm 1 can use up to four channels at the same time. uart0 and uart1 transfer data using the txd0, txd1, rxd0, and rxd1 pins. csi0 and csi1 transfer data using the so0, so1, si0, si1, sck0, and sck1 pins. (12) a/d converter the v850es/pm1 has 12 analog input pins and a si x-channel 16-bit a/d converter that uses a ? conversion method. it also has a function to input/output a refere nce voltage, and includes six a/d conversion result registers. (13) rom correction this is a function to replace part of the program in the mask rom with program in the internal ram for execution. the program can be corrected at up to four places. (14) ports some port pins have a control function as well as a general-purpose port function, as shown below. port i/o alternate function p0 4-bit i/o nmi, external interrupt, timer input p1 5-bit i/o pwm output, timer i/o p2 2-bit i/o timer output p3 7-bit i/o serial interface, timer input, timer trigger p4 7-bit i/o serial interface, timer output, timer trigger p9 16-bit i/o external address bus, timer input pcm 2-bit i/o external bus control signal pcs 3-bit i/o chip select output pct 3-bit i/o external bus control signal pdh 3-bit i/o external address bus pdl 16-bit i/o external data bus
user?s manual u16237ej3v0ud 21 chapter 2 pin functions 2.1 pin function list this chapter explains the names and f unctions of the pins in the v850es/pm1, classified into port pins and non- port pins. two power supplies are availabl e for the pin i/o buffers: av dd and ev dd . the relationship between the power supplies and pins is shown below. table 2-1. i/o buffer power supply for each pin power supply corresponding pin av dd anin0, anin1 (n = 0 to 5) ev dd ports 0 to 4, 9, cm, cs, ct, dh, dl, reset
chapter 2 pin functions user?s manual u16237ej3v0ud 22 (1) port pins (1/2) pin name pin no. i/o on-chip pull-up resistor function alternate function p00 79 nmi p01 78 intp0 p02 77 intp1 p03 76 i/o provided port 0 4-bit i/o port input/output can be specified in 1-bit units. intp2/ti20 p10 6 pwm0 p11 7 to00/pwm1 p12 8 to01/pwm2 p13 9 to20/pwm3 p14 10 i/o provided port 1 5-bit i/o port input/output can be specified in 1-bit units. to21/ti21 p20 36 to02 p21 37 i/o provided port 2 2-bit i/o port input/output can be specified in 1-bit units. to03 p30 5 rxd0 p31 4 txd0 p32 3 si1 p33 2 so1 p34 1 sck1 p35 100 intp100/ti10/tclr10 p36 99 i/o provided port 3 7-bit i/o port input/output can be specified in 1-bit units. intp110/ti11/tclr11 p40 69 si0 p41 70 so0 p42 71 sck0 p43 72 rxd1 p44 73 txd1 p45 74 intp101/to10 p46 75 i/o provided port 4 7-bit i/o port input/output can be specified in 1-bit units. intp111/to11 p90 20 a0 p91 21 a1 p92 22 a2 p93 23 a3 p94 24 a4 p95 25 a5 p96 26 a6 p97 27 a7 p98 28 a8/ti030 p99 29 a9/ti031 p910 30 a10/ti020 p911 31 a11/ti021 p912 32 a12/ti010 p913 33 a13/ti011 p914 34 a14/ti000 p915 35 i/o none port 9 16-bit i/o port input/output can be specified in 1-bit units. a15/ti001
chapter 2 pin functions user?s manual u16237ej3v0ud 23 (2/2) pin name pin no. i/o on-chip pull-up resistor function alternate function pcm0 41 wait pcm1 40 i/o none port cm 2-bit i/o port input/output can be specified in 1-bit units. clkout pcs0 66 cs0 pcs1 67 cs1 pcs2 68 i/o none port cs 3-bit i/o port input/output can be specified in 1-bit units. cs2 pct0 45 wr0 pct1 46 wr1 pct4 47 i/o none port ct 3-bit i/o port input/output can be specified in 1-bit units. rd pdh0 42 a16 pdh1 43 a17 pdh2 44 i/o none port dh 3-bit i/o port input/output can be specified in 1-bit units. a18 pdl0 48 d0 pdl1 49 d1 pdl2 50 d2 pdl3 51 d3 pdl4 52 d4 pdl5 53 d5 pdl6 54 d6 pdl7 55 d7 pdl8 56 d8 pdl9 57 d9 pdl10 58 d10 pdl11 59 d11 pdl12 60 d12 pdl13 61 d13 pdl14 62 d14 pdl15 63 i/o none port dl 16-bit i/o port input/output can be specified in 1-bit units. d15
chapter 2 pin functions user?s manual u16237ej3v0ud 24 (2) non-port pins (1/3) pin name pin no. i/o on-chip pull-up resistor function alternate function a0 20 p90 a1 21 p91 a2 22 p92 a3 23 p93 a4 24 p94 a5 25 p95 a6 26 p96 a7 27 p97 a8 28 p98/ti030 a9 29 p99/ti031 a10 30 p910/ti020 a11 31 p911/ti021 a12 32 p912/ti010 a13 33 p913/ti011 a14 34 p914/ti000 a15 35 p915/ti001 a16 42 pdh0 a17 43 pdh1 a18 44 output none address bus for external memory pdh2 d0 to d15 48 to 63 i/o none data bus for external memory pdl0 to pdl15 ani00 82 ? ani01 83 ? ani10 95 ? ani11 94 ? ani20 84 ? ani21 85 ? ani30 93 ? ani31 92 ? ani40 86 ? ani41 87 ? ani50 91 ? ani51 90 input none analog voltage input for a/d converter ? av dd 81 ? ? positive power supply for a/d converter (same potential as v dd ) ? av refin 88 input reference voltage input for a/d converter ? av refout 89 output ? reference voltage output for a/d converter ? av ss 97 ? ? ground potential for a/d converter (same potential as v ss ) ? clkout 40 output none internal system clock output pcm1 cs0 to cs2 66 to 68 output none chip select output pcs0 to pcs2 ev dd 19, 39, 65 ? ? positive power supply for external device (same potential as v dd ) ? ev ss 18, 38, 64 ? ? ground potential for external device (same potential as v ss ) ?
chapter 2 pin functions user?s manual u16237ej3v0ud 25 (2/3) pin name pin no. i/o on-chip pull-up resistor function alternate function ic0 96 ? ? internally connected (connect this pin directly to av ss ) ? ic1 98 ? ? internally connected (connect this pin directly to v ss ) ? intp0 78 p01 intp1 77 p02 intp2 76 input provided external interrupt request input (maskable, analog noise elimination) p03/ti20 intp100 100 p35/ti10/tclr10 intp101 74 capture trigger input (tm10) p45/to10 intp110 99 p36/ti11/tclr11 intp111 75 input provided capture trigger input (tm11) p46/to11 mode 80 input none operation mode specification ? nmi 79 input provided external interrupt request input (non-maskable, analog noise elimination) p00 pwm0 6 p10 pwm1 7 p11/to00 pwm2 8 p12/to01 pwm3 9 output provided pwm output p13/to20 rd 47 output none read strobe signal output for external memory pct4 reset 15 input ? system reset input ? rxd0 5 serial receive data input (uart0) p30 rxd1 72 input provided serial receive data input (uart1) p43 sck0 71 serial clock i/o (csi0) p42 sck1 1 i/o provided serial clock i/o (csi1) p34 si0 69 serial receive data input (csi0) p40 si1 3 input provided serial receive data input (csi1) p32 so0 70 serial transmit data output (csi0) p41 so1 2 output provided serial transmit data output (csi1) p33 tclr10 100 timer clear input (tm10) p35/intp100/ti10 tclr11 99 input provided timer clear input (tm11) p36/intp110/ti11 ti000 34 external event/clock input (tm00) p914/a14 ti001 35 external event input (tm00) p915/a15 ti010 32 external event/clock input (tm01) p912/a12 ti011 33 external event input (tm01) p913/a13 ti020 30 external event/clock input (tm02) p910/a10 ti021 31 external event input (tm02) p911/a11 ti030 28 external event/clock input (tm03) p98/a8 ti031 29 input none external event input (tm03) p99/a9 ti10 100 external clock input (tm10) p35/intp100/tclr10 ti11 99 input provided external clock input (tm11) p36/intp110/tclr11 ti20 76 external clock input (tm20) p03/intp2 ti21 10 input provided external clock input (tm21) p14/to21 to00 7 timer output (tm00) p11/pwm1 to01 8 timer output (tm01) p12/pwm2 to02 36 output provided timer output (tm02) p20
chapter 2 pin functions user?s manual u16237ej3v0ud 26 (3/3) pin name pin no. i/o on-chip pull-up resistor function alternate function to03 37 timer output (tm03) p21 to10 74 timer output (tm10) p45/intp101 to11 75 output provided timer output (tm11) p46/intp111 to20 9 output provided timer output (tm20) p13/pwm3 to21 10 output provided timer output (tm21) p14/ti21 txd0 4 serial transmit data output (uart0) p31 txd1 73 output provided serial transmit data output (uart1) p44 v dd 11 ? ? positive power supply for internal ? v ss 12 ? ? ground potential for internal ? wait 41 input none external wait input pcm0 wr0 45 write strobe for external memory (lower 8 bits) pct0 wr1 46 output none write strobe for external memory (higher 8 bits) pct1 x1 13 input ? x2 14 ? none connection of resonator for main clock ? xt1 16 input ? xt2 17 ? none connection of resonator for subclock ?
chapter 2 pin functions user?s manual u16237ej3v0ud 27 2.2 pin status the operating status of each pin in each operation mode is shown below. table 2-2. operating status of each pin in each operation mode bus control pins reset note 1 halt mode idle and stop modes idle state note 2 d0 to d15 hi-z hi-z hi-z retained a16 to a18 hi-z undefined hi-z retained a0 to a15 hi-z undefined hi-z retained wait hi-z ? ? ? clkout hi-z operates l operates cs0 to cs2 hi-z h h retained wr0, wr1 hi-z h h h rd hi-z h h h notes 1. because the bus control pins function alternately as port pins, they are initialized to the input mode (port mode) in the single chip mode. signals other than the clkout signal are initializ ed to the control mode while the romless mode is reset. 2. indicates the pin status in the idle st ate that is inserted after the t2 state. remark hi-z: high impedance retained: status in external bus cycle immediately before is retained. l: low-level output h: high-level output ? : input not sampled (not acknowledged)
chapter 2 pin functions user?s manual u16237ej3v0ud 28 2.3 types of pin i/o circuits, i/o buffer po wer supplies, and connection of unused pins (1/2) pin alternate function pin no. i/o circuit type recommended connection p00 nmi 79 p01, p02 intp0, intp1 78, 77 p03 intp2/ti20 76 8-a p10 pwm0 6 p11 to00/pwm1 7 p12 to01/pwm2 8 p13 to20/pwm3 9 5-a p14 to21/ti21 10 8-a p20, p21 to02, to03 36, 37 5-a p30 rxd0 5 8-a p31 txd0 4 5-a p32 si1 3 8-a p33 so1 2 5-a p34 sck1 1 p35 intp100/ti10/tclr10 100 p36 intp110/ti11/tclr11 99 p40 si0 69 8-a p41 so0 70 5-a p42 sck0 71 p43 rxd1 72 8-a p44 txd1 73 5-a p45 intp101/to10 74 p46 intp111/to11 75 8-a input: independently connect to ev dd or ev ss via a resistor. output: leave open. p90 to p97 a0 to a7 20 to 27 5 p98 a8/ti030 28 p99 a9/ti031 29 p910 a10/ti020 30 p911 a11/ti021 31 p912 a12/ti010 32 p913 a13/ti011 33 p914 a14/ti000 34 p915 a15/ti001 35 8 pcm0 wait 41 pcm1 clkout 40 pcs0 to pcs2 cs0 to cs2 66 to 68 pct0, pct1 wr0, wr1 45, 46 pct4 rd 47 pdh0 to pdh2 a16 to a18 42 to 44 pdl0 to pdl15 d0 to d15 48 to 63 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open.
chapter 2 pin functions user?s manual u16237ej3v0ud 29 (2/2) pin alternate function pin no. i/o circuit type recommended connection ani00, ani01, ani10, ani11, ani20, ani21, ani30, ani31, ani40, ani41, ani50, ani51 ? 82 to 87, 90 to 95 35 connect to av dd or av ss via a resistor. av dd ? 81 ? ? av refin ? 88 ? connect to av ss via a resistor. av refout ? 89 ? leave open. av ss ? 97 ? ? ev dd ? 19, 39, 65 ? ? ev ss ? 18, 38, 64 ? ? ic0, ic1 ? 96, 98 ? ? reset ? 15 2 ? mode ? 80 2 ? v dd ? 11 ? ? v ss ? 12 ? ? x1 ? 13 ? ? x2 ? 14 ? ? xt1 ? 16 16 connect to v ss via a resistor. xt2 ? 17 16 leave open.
chapter 2 pin functions user?s manual u16237ej3v0ud 30 figure 2-1. pin i/o circuits type 2 schmitt-triggered input with hysteresis characteristics. type 5 type 8-a in data output disable p-ch in/out ev dd n-ch ev ss input enable type 5-a type 8 data output disable p-ch in/out ev dd n-ch ev ss input enable p-ch ev dd pull-up enable type 16 type 35 p-ch feedback cut-off xt1 xt2 + + in0 in1 av dd ? ? av dd pull-up enable data output disable ev dd p-ch ev dd p-ch in/out n-ch ev ss av ss data output disable ev dd ev ss p-ch in/out n-ch
user?s manual u16237ej3v0ud 31 chapter 3 cpu function the cpu of the v850es/pm1 is based on risc architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 features minimum instruction execution time: 50 ns (at 20 mhz operation: 3.0 to 3.6 v) 100 ns (at 10 mhz operation: 2.7 to 3.6 v) 30.5 s (with subclock (f xt ) = 32.768 khz operation: 2.2 to 3.6 v) memory space program (physical address) space: 64 mb linear data (logical address) space: 4 gb linear ? memory block division function: 2, 2, 4 mb/total: 3 blocks each block can be accessed in 512 kb units. general-purpose registers: 32 bits 32 registers internal 32-bit architecture 5-stage pipeline control multiplication/division instruction saturation operation instruction 32-bit shift instruction: 1 clock load/store instruction with long/short format four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1
chapter 3 cpu function user?s manual u16237ej3v0ud 32 3.2 cpu register set the registers of the v850e s/pm1 can be classified into two types : general-purpose program registers and dedicated system registers. all the registers are 32 bits wide. for details, refer to the v850es architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register)
chapter 3 cpu function user?s manual u16237ej3v0ud 33 3.2.1 program register set the program registers include general-p urpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are av ailable. any of these registers can be used to store a data variable or an address variable. however, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the sld and sst instructions as a base pointer when these inst ructions access the memory. r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. when using these registers, save their contents for protection, and then restore the contents after using the registers. r2 is sometimes used by the real-time os. if the real-time os does not use r2, it can be used as a register for variables. table 3-1. program registers name usage operation r0 zero register always holds 0. r1 assembler-reserved register used as work ing register to create 32-bit immediate data r2 register for address/data variable (if real-time os does not use r2) r3 stack pointer used to create a stack frame when a function is called r4 global pointer used to access a global variable in the data area r5 text pointer used as register that i ndicates the beginning of a text area (area where program codes are located) r6 to r29 register for address/data variable r30 element pointer used as base pointer to access memory r31 link pointer used when t he compiler calls a function pc program counter holds the instruction address during program execution (2) program counter (pc) the program counter holds the instructi on address during program execution. the lower 26 bits of this register are valid. bits 31 to 26 are fixed to 0. a carry from bit 25 to 26 is ignored even if it occurs. bit 0 is fixed to 0. this means that execution cannot branch to an odd address. 31 26 25 1 0 pc fixed to 0 instruction address during program execution 0 default value 00000000h
chapter 3 cpu function user?s manual u16237ej3v0ud 34 3.2.2 system register set the system registers control the status of the cpu and hold interrupt information. these registers can be read or written by using system register load/sto re instructions (ldsr and stsr), using the system register numbers listed below. table 3-2. system register numbers operand specification system register number system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 1 interrupt status saving register (eipsw) note 1 2 nmi status saving register (fepc) 3 nmi status saving register (fepsw) 4 interrupt source register (ecr) 5 program status word (psw) 6 to 15 reserved for future function expansion (operation is not guaranteed if these registers are accessed) 16 callt execution status saving register (ctpc) 17 callt execution status saving register (ctpsw) 18 exception/debug trap status saving register (dbpc) note 2 note 2 19 exception/debug trap status saving register (dbpsw) note 2 note 2 20 callt base pointer (ctbp) 21 to 31 reserved for future function expansion (operation is not guaranteed if these registers are accessed) notes 1. because only one set of this register is available, t he contents of this register must be saved by program if multiple interrupts are enabled. 2. these registers can be accessed only during the interval between the execution of the dbtrap instruction or illegal opcode and the dbret instruction. caution even if eipc or fepc, or bit 0 of ctpc is set to 1 by the ldsr instruction, bit 0 is ignored when execution is returned to the main routine by the reti instruction after interrupt ser vicing (this is because bit 0 of the pc is fixed to 0). set an even value to eipc, fepc, and ctpc (bit 0 = 0). remark : can be accessed : access prohibited
chapter 3 cpu function user?s manual u16237ej3v0ud 35 (1) interrupt status saving registers (eipc and eipsw) eipc and eipsw are used to save the status when an interrupt occurs. if a software exception or a maskable interrupt occurs, th e contents of the program counter (pc) are saved to eipc, and the contents of the program status word ( psw) are saved to eipsw (these contents are saved to the nmi status saving registers (fepc and f epsw) if a non-maskable interrupt occurs). the address of the instruction next to the one of the instruction under exec ution, except some instructions (see 16.8 periods in which interrupts are not acknowledged by cpu ), is saved to eipc when a software exception or a maskable interrupt occurs. the current contents of the psw are saved to eipsw. because only one set of interrupt status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are reserved for future function expansion (these bits are always fixed to 0). the values of eipc and eipsw are restored to the pc and psw respectively by the reti instruction. 31 0 eipc (saved contents of pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (saved contents of psw) 0 0 default value 000000xxh (x: undefined) 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (2) nmi status saving registers (fepc and fepsw) fepc and fepsw are used to save the status when a non-maskable interrupt (nmi) occurs. if an nmi occurs, the contents of the program counter (pc) are saved to fepc, and those of the program status word (psw) are saved to fepsw. the address of the instruction next to the one of the instruction under exec ution, except some instructions, is saved to fepc when an nmi occurs. the current contents of t he psw are saved to fepsw. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served for future function expansion (these bits are always fixed to 0). 31 0 fepc (contents of pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (contents of psw) 0 0 default value 000000xxh (x: undefined) 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
chapter 3 cpu function user?s manual u16237ej3v0ud 36 (3) interrupt source register (ecr) the interrupt source register (ecr) hol ds the source of an exception or in terrupt if an exception or interrupt occurs. this register holds the exception code of each interrupt source. because this register is a read-only register, data cannot be written to this register using the ldsr instruction. 31 0 ecr fecc eicc default value 00000000h 16 15 bit position bit name meaning 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupt (4) program status word (psw) the program status word (psw) is a collection of flags that indicate th e status of the program (result of instruction execution) and the status of the cpu. if the contents of a bit of this regi ster are changed by using the ldsr instruction, the new contents are validated immediately after completion of ldsr instruct ion execution. during the period in which the psw is being accessed by the ldsr instruction, ackn owledgment of interrupt requests is held pending. bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0). (1/2) 31 0 psw rfu default value 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name meaning 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that a non-maskable interrupt (nmi) is being serviced. this bit is set to 1 when an nmi request is acknowledged, disabling multiple interrupts. 0: nmi is not being serviced. 1: nmi is being serviced. 6 ep indicates that an exception is being proces sed. this bit is set to 1 when an exception occurs. even if this bit is set, interrupt requests are acknowledged. 0: exception is not being processed. 1: exception is being processed. 5 id indicates whether a maskable interrupt can be acknowledged. 0: interrupt enabled (ei) 1: interrupt disabled (di)
chapter 3 cpu function user?s manual u16237ej3v0ud 37 (2/2) bit position flag name meaning 4 sat note indicates that the result of a saturation operation has overflowed and is saturated. because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. use the ldsr instruction to clear this bit. th is flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: not saturated 1: saturated 3 cy indicates whether a ca rry or a borrow occurs as a result of an operation. 0: carry or borrow does not occur. 1: carry or borrow occurs. 2 ov note indicates whether an overflow occurs during operation. 0: overflow does not occur. 1: overflow occurs. 1 s note indicates whether the result of an operation is negative. 0: the result is positive or 0. 1: the result is negative. 0 z indicates whether the result of an operation is 0. 0: the result is not 0. 1: the result is 0. note the result of the operation that has performed satura tion processing is determined by the contents of the ov and s flags. the sat flag is set to 1 only when the ov flag is set to 1 when a saturation operation is performed. flag status status of operation result sat ov s result of operation of saturation processing maximum positive value is exceeded. 1 1 0 7fffffffh maximum negative value is exceeded. 1 1 1 80000000h positive (maximum value is not exceeded) 0 negative (maximum value is not exceeded) holds value before operation 0 1 operation result itself
chapter 3 cpu function user?s manual u16237ej3v0ud 38 (5) callt execution status saving registers (ctpc and ctpsw) ctpc and ctpsw are callt execut ion status saving registers. when the callt instruction is execut ed, the contents of the program co unter (pc) are saved to ctpc, and those of the program status wo rd (psw) are saved to ctpsw. the contents saved to ctpc are the address of the inst ruction next to callt. the current contents of t he psw are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are reserved for future function expansion (fixed to 0). 31 0 ctpc (contents of pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (contents of psw) 0 0 default value 000000xxh (x: undefined) 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (6) exception/debug trap status saving registers (dbpc and dbpsw) dbpc and dbpsw are exception/debug trap status saving registers. if an exception trap or debug trap occurs, the contents of the program counter (pc) are saved to dbpc, and those of the program status word (psw) are saved to dbpsw. the contents to be saved to dbpc are the address of the instruction next to the one that is executed when an exception trap or debug trap occurs. the current contents of t he psw are saved to dbpsw. this register can be read only during the interval bet ween the execution of the db trap instruction or illegal opcode and dbret instruction. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are reserved for future function expansion (fixed to 0). 31 0 dbpc (contents of pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (contents of psw) 0 0 default value 000000xxh (x: undefined) 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
chapter 3 cpu function user?s manual u16237ej3v0ud 39 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify a tabl e address or generate a target address (bit 0 is fixed to 0). bits 31 to 26 of this register are reserved for future function expansion (fixed to 0). 31 0 ctbp (base address) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0
chapter 3 cpu function user?s manual u16237ej3v0ud 40 3.3 operation modes 3.3.1 operation modes the v850es/pm1 has the following operation modes. (1) single-chip mode in this mode, each pin related to the bus interface is set to the port mode after system reset has been released. execution branches to the reset entry address of the intern al rom, and then instruction processing is started. (2) romless mode of the pins related to the bus interface, only the pcm1 pi n is set in the port mode and the other pins are set in the control mode after the system reset signal has been released. the program branches to the reset entry address of an external device (memory) and starts instru ction processing. instruction fetch or data access to the internal rom is impossible. the default value of the following regi sters differs depending on the mode. operation mode pmcdl pmcdh pmccs pmcct pmccm romless mode ffffh 07h 07h 13h 01h single-chip mode 0000h 00h 00h 00h 00h 3.3.2 specifying operation mode the operation mode is specified according to the status of the mode pin. fix the level of this pin in the application system and do not change it during operation, otherwise the operation will not be guaranteed. mode operation mode remark l romless mode 16-bit data bus h single-chip mode ? caution be sure to set these pins of the pd703228gc-003-8eu and pd703228gc-004-8eu-a to l (low level). remark l: low-level input h: high-level input
chapter 3 cpu function user?s manual u16237ej3v0ud 41 3.4 address space 3.4.1 cpu address space for instruction addressing, up to 8 mb of linear addre ss space (program space) and an internal ram area are supported. for operand addressing (data access), up to 4 gb of a linear address space (data space) is supported. the 4 gb address space, however, is viewed as 64 images of a 64 mb physical address space. this means that the same 64 mb physical address space is accessed regardless of the values of bits 31 to 26. figure 3-1. image on address space program space internal ram area use prohibited area use prohibited area external memory area internal rom area (external memory area) data space image 63 image 1 image 0 on-chip peripheral i/o area internal ram area use prohibited area external memory area internal rom area (external memory area) 8 mb 4 gb 64 mb 64 mb
chapter 3 cpu function user?s manual u16237ej3v0ud 42 3.4.2 wrap-around of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. the higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. therefore, the lowest address of the program space, 00000000h, and the highest addres s, 03ffffffh, are contiguous addresses. that the lo west address and the highest address of the program space are contiguous in this way is called wrap-around. caution because the 4 kb area of addresses 03fff000h to 03ffffffh is an on-chip peripheral i/o area, instructions cannot be fetc hed from this area. therefore , do not execute an operation in which the result of a branch addr ess calculation affects this area. program space program space (+) direction ( ? ) direction 00000001h 00000000h 03ffffffh 03fffffeh (2) data space the result of an operand address calculation oper ation that exceeds 32 bits is ignored. therefore, the lowest address of the data space, 00000000h, and the highest address, ffffffffh, are contiguous, and wrap-around occurs at the boundary of these addresses. data space data space (+) direction ( ? ) direction 00000001h 00000000h ffffffffh fffffffeh
chapter 3 cpu function user?s manual u16237ej3v0ud 43 3.4.3 memory map the v850es/pm1 reserves the areas shown in the following. figure 3-2. data memory map (physical addresses) (80 kb) use prohibited internal rom area note 2 (1 mb) external memory area note 1 (1 mb) internal ram area (10 kb) on-chip peripheral i/o area (4 kb) use prohibited external memory area note 1 (4 mb) external memory area note 1 (2 mb) (2 mb) cs0 cs1 cs2 3ffffffh 3fec000h 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h 3febfffh 3ffffffh 3fff000h 3ffefffh 3ffc800h 3ffc7ffh 3fec000h 01fffffh 0100000h 00fffffh 0000000h notes 1. each of these areas is a 512 kb spac e of 0100000h to 017ffffh, 0200000h to 027ffffh, or 0400000h to 047ffffh (01800 00h to 01fffffh, 0280000h to 03fffffh, and 0480000h to 07fffffh are an image). 2. fetch access and read access to addresses 000 0000h to 00fffffh is made to the internal rom area. however, data write access to these addresses is made to the external memory area.
chapter 3 cpu function user?s manual u16237ej3v0ud 44 figure 3-3. program memory map internal ram area (10 kb) use prohibited (program fetch prohibited area) use prohibited (program fetch prohibited area) external memory area note (4 mb) external memory area note (1 mb) external memory area note (2 mb) internal rom area (1 mb) cs0 cs1 cs2 03ffffffh 03fff000h 03ffefffh 3ffc800h 3ffc7ffh 00800000h 007fffffh 00400000h 003fffffh 00200000h 001fffffh 00100000h 000fffffh 00000000h note each of these areas is a 512 kb space of 0100000h to 017ffffh, 0200000h to 027ffffh, or 0400000h to 047ffffh (0180000h to 01fffffh , 0280000h to 03fffffh, and 0480000h to 07fffffh are an image).
chapter 3 cpu function user?s manual u16237ej3v0ud 45 3.4.4 areas (1) internal rom area (a) memory map 1 mb of addresses 0000000h to 00fffffh is reserved as the internal rom area. 128 kb are mapped to addresses 000 000h to 01ffffh as the physical internal rom (mask rom). remark the internal rom area is not available in the romless mode. figure 3-4. internal rom area xx020000h xx01ffffh xx000000h xx0fffffh access-prohibited area internal rom (2) internal ram area 60 kb of addresses 3ff0000h to 3ffefffh ar e reserved as the internal ram area. the v850es/pm1 maps 10 kb of addresses 3ffc800h to 3ffefffh as physical internal ram. figure 3-5. internal ram area (10 kb) internal ram area (10 kb) access prohibited area 3ffc800h 3ffefffh 3ff0000h 3ffc7ffh fffc800h fffefffh fff0000h fffc7ffh plysical address space logical address space
chapter 3 cpu function user?s manual u16237ej3v0ud 46 (3) on-chip peripheral i/o area 4 kb of addresses 3fff000h to 3ffffffh are allo cated as the on-chip peripheral i/o area. figure 3-6. on-chip peripheral i/o area on-chip peripheral i/o area (4 kb) 3ffffffh 3fff000h fffffffh ffff000h plysical address space logical address space peripheral i/o registers that have functions to specif y the operation mode for and mo nitor the status of the on- chip peripheral i/o are mapped to the on-chip periphe ral i/o area. program cannot be fetched from this area. cautions 1. when a register is accessed in word units, a word area is accessed twice in halfword units in the order of lower area and higher area, with the lower 2 bits of the address ignored. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits are undefined when the register is read , and data is written to the lower 8 bits. 3. addresses not defined as registers are r eserved for future expansion. the operation is undefined and not guaranteed when these addresses are accessed. (4) external memory area 7 mb (0100000h to 07fffffh) are allocated as the external memory area. for details, see chapter 5 bus control function .
chapter 3 cpu function user?s manual u16237ej3v0ud 47 3.4.5 recommended use of address space the architecture of the v850es/pm1 requ ires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. the address stored in this pointer 32 kb can be directly accessed by an instruction for operand data. beca use the number of general-purpose registers that can be used as a pointer is limited, however, by keeping the pe rformance from dropping during address calculation when a pointer value is changed, as many general-purpose registers as possible can be secured for variables, and the program size can be reduced. (1) program space of the 32 bits of the program counter (p c), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. regarding the program space, therefore, a 64 mb spac e of contiguous addresses starting from 00000000h unconditionally corresponds to the memory map. to use the internal ram area as the program space, access addresses 3ffc800h to 3ffefffh. (2) data space with the v850es/pm1, it seems t hat there are sixty-four 64 mb addr ess spaces on the 4 gb cpu address space. therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. example : an application example of wrap-around is shown below. internal rom area on-chip peripheral i/o area access prohibited area internal ram area 3 2 kb 4 kb 10 kb 18 kb (r = ) 0001ffffh 00007fffh 00000000h fffff000h ffffefffh ffffc800h ffffc7ffh ffff8000h if r = r0 (zero register) is specified for the ld/st disp16 [r] instruction, a range of addresses 00000000h 32 kb can be addressed by sign-extended disp16. all the resources of the internal hardware can be addressed by one pointer. the zero register (r0) is a register fixed to 0 by har dware, and practically eliminates the need for registers dedicated to pointers.
chapter 3 cpu function user?s manual u16237ej3v0ud 48 figure 3-7. recommended memory map data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom external memory use prohibited external memory use prohibited internal ram on-chip peripheral i/o note program space, 64 mb internal rom internal rom ffffffffh fffff000h ffffefffh ffffc000h ffffbfffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ffc800h 03ffc7ffh 03fec000h 03febfffh 00800000h 007fffffh 00100000h 000fffffh 00000000h xfffffffh xffff000h xfffefffh xfffc800h xfffc7ffh xffec000h xffebfffh x0100000h x00fffffh x0000000h note access to this area is prohibited. to access the on-chip peripheral i/o in this area, specify addresses ffff000h to fffffffh. remark indicates the recommended area.
chapter 3 cpu function user?s manual u16237ej3v0ud 49 3.4.6 peripheral i/o registers (1/6) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff004h port dl pdl 0000h note 1 fffff004h port dll pdll fffff005h port dlh pdlh fffff006h port dh pdh fffff008h port cs pcs fffff00ah port ct pct fffff00ch port cm pcm 00h note 1 fffff024h port dl mode register pmdl ffffh fffff024h port dll mode register pmdll fffff025h port dlh mode register pmdlh fffff026h port dh mode register pmdh fffff028h port cs mode register pmcs fffff02ah port ct mode register pmct fffff02ch port cm mode register pmcm ffh fffff044h port dl mode control register pmcdl ffffh note 2 fffff044h port dll mode control register pmcdll ffh note 2 fffff045h port dlh mode control register pmcdlh ffh note 2 fffff046h port dh mode control register pmcdh 07h note 2 fffff048h port cs mode control register pmccs 07h note 2 fffff04ah port ct mode control register pmcct 13h note 2 fffff04ch port cm mode control register pmccm 01h note 2 fffff066h bus size configuration register bsc 5555h fffff06eh system wait control register vswc 77h fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l fffff101h interrupt mask register 0h imr0h ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l fffff103h interrupt mask register 1h imr1h ffh fffff110h interrupt control register wdtic fffff112h interrupt control register pic0 fffff114h interrupt control register pic1 fffff116h interrupt control register pic2 fffff118h interrupt control register adic fffff11ah interrupt control register rtcic fffff11ch interrupt control register tmic000 fffff11eh interrupt control register tmic001 fffff120h interrupt control register tmic010 fffff122h interrupt control register tmic011 fffff124h interrupt control register tmic020 fffff126h interrupt control register tmic021 r/w 47h notes 1. the value of the output latch is 00h or 0000h. when input, the status of the pin is read. 2. this is a value in the romless mode. it is 00h or 0000h in the single-chip mode.
chapter 3 cpu function user?s manual u16237ej3v0ud 50 (2/6) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff128h interrupt control register tmic030 fffff12ah interrupt control register tmic031 fffff12ch interrupt control register ccic100 fffff12eh interrupt control register ccic101 fffff130h interrupt control register ovfic10 fffff132h interrupt control register ccic110 fffff134h interrupt control register ccic111 fffff136h interrupt control register ovfic11 fffff138h interrupt control register tmic20 fffff13ah interrupt control register tmic21 fffff13ch interrupt control register csiic0 fffff13eh interrupt control register csiic1 fffff140h interrupt control register sreic0 fffff142h interrupt control register sric0 fffff144h interrupt control register stic0 fffff146h interrupt control register sreic1 fffff148h interrupt control register sric1 fffff14ah interrupt control register stic1 fffff14ch interrupt control register rovic r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc fffff200h a/d converter mode register adm fffff201h a/d clock delay setting register adly fffff202h high-pass filter control register 0 hpfc0 r/w 00h fffff204h a/d conversion result register 0 adcr0 fffff206h a/d conversion result register 1 adcr1 fffff208h a/d conversion result register 2 adcr2 fffff20ah a/d conversion result register 3 adcr3 fffff20ch a/d conversion result register 4 adcr4 fffff20eh a/d conversion result register 5 adcr5 r 0000h fffff400h port 0 p0 fffff402h port 1 p1 fffff404h port 2 p2 fffff406h port 3 p3 fffff408h port 4 p4 00h note fffff412h port 9 p9 0000h note fffff412h port 9l p9l fffff413h port 9h p9h 00h note fffff420h port 0 mode register pm0 fffff422h port 1 mode register pm1 fffff424h port 2 mode register pm2 r/w ffh note the value of the output latch is 00h or 0000h. when input, the status of the pin is read.
chapter 3 cpu function user?s manual u16237ej3v0ud 51 (3/6) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff426h port 3 mode register pm3 fffff428h port 4 mode register pm4 ffh fffff432h port 9 mode register pm9 ffffh fffff432h port 9 mode register l pm9l fffff433h port 9 mode register h pm9h ffh fffff440h port 0 mode control register pmc0 fffff442h port 1 mode control register pmc1 fffff444h port 2 mode control register pmc2 fffff446h port 3 mode control register pmc3 fffff448h port 4 mode control register pmc4 00h fffff452h port 9 mode control register pmc9 ffffh note fffff452h port 9 mode control register l pmc9l fffff453h port 9 mode control register h pmc9h ffh note fffff460h port 0 function control register pfc0 fffff462h port 1 function control register pfc1 fffff466h port 3 function control register pfc3 fffff468h port 4 function control register pfc4 00h fffff472h port 9 function control register pfc9 0000h fffff472h port 9 function control register l pfc9l fffff473h port 9 function control register h pfc9h 00h fffff484h data wait control register 0 dwc0 7777h fffff488h address wait control register awc ffffh fffff48ah bus cycle control register bcc r/w aaaah fffff5c0h 16-bit timer counter 00 tm00 r fffff5c2h 16-bit timer capture/compare register 000 cr000 fffff5c4h 16-bit timer capture/compare register 001 cr001 0000h fffff5c6h 16-bit timer mode control register 00 tmc00 fffff5c7h prescaler mode register 00 prm00 fffff5c8h capture/compare control register 00 crc00 fffff5c9h 16-bit timer output control register 00 toc00 r/w 00h fffff5d0h 16-bit timer counter 01 tm01 r fffff5d2h 16-bit timer capture/compare register 010 cr010 fffff5d4h 16-bit timer capture/compare register 011 cr011 0000h fffff5d6h 16-bit timer mode control register 01 tmc01 fffff5d7h prescaler mode register 01 prm01 fffff5d8h capture/compare control register 01 crc01 fffff5d9h 16-bit timer output control register 01 toc01 r/w 00h fffff5e0h 16-bit timer counter 02 tm02 r fffff5e2h 16-bit timer capture/compare register 020 cr020 fffff5e4h 16-bit timer capture/compare register 021 cr021 0000h fffff5e6h 16-bit timer mode control register 02 tmc02 fffff5e7h prescaler mode register 02 prm02 fffff5e8h capture/compare control register 02 crc02 r/w 00h note this is a value in the romless mode. it is 00h or 0000h in the single-chip mode.
chapter 3 cpu function user?s manual u16237ej3v0ud 52 (4/6) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff5e9h 16-bit timer output control register 02 toc02 r/w 00h fffff5f0h 16-bit timer counter 03 tm03 r fffff5f2h 16-bit timer capture/compare register 030 cr030 fffff5f4h 16-bit timer capture/compare register 031 cr031 0000h fffff5f6h 16-bit timer mode control register 03 tmc03 fffff5f7h prescaler mode register 03 prm03 fffff5f8h capture/compare control register 03 crc03 fffff5f9h 16-bit timer output control register 03 toc03 r/w 00h fffff600h 16-bit timer counter 10 tm10 r fffff602h 16-bit timer capture/compare register 100 cc100 fffff604h 16-bit timer capture/compare register 101 cc101 0000h fffff606h 16-bit timer mode control register 100 tmc100 00h fffff608h 16-bit timer mode control register 101 tmc101 20h fffff609h valid edge select register 10 ses10 r/w 00h fffff610h 16-bit timer counter 11 tm11 r fffff612h 16-bit timer capture/compare register 110 cc110 fffff614h 16-bit timer capture/compare register 111 cc111 0000h fffff616h 16-bit timer mode control register 110 tmc110 00h fffff618h 16-bit timer mode control register 111 tmc111 20h fffff619h valid edge select register 11 ses11 r/w 00h fffff640h 16-bit timer counter 2 tm2 0000h fffff640h 8-bit timer counter 20 tm20 fffff641h 8-bit timer counter 21 tm21 r 00h fffff642h 16-bit timer compare register 2 cr2 0000h fffff642h 8-bit timer compare register 20 cr20 fffff643h 8-bit timer compare register 21 cr21 00h fffff644h timer clock select register 2 tcl2 0000h fffff644h timer clock select register 20 tcl20 fffff645h timer clock select register 21 tcl21 00h fffff646h 16-bit timer mode control register 2 tmc2 0000h fffff646h 8-bit timer mode control register 20 tmc20 fffff647h 8-bit timer mode control register 21 tmc21 00h fffff680h rtc control register rtcc 8x80h fffff680h rtc control register 0 rtcc0 80h fffff681h rtc control register 1 rtcc1 r/w 8xh fffff682h sub-count register subc fffff682h sub-count register l subcl fffff683h sub-count register h subch fffff684h minute/second count register secmin fffff684h second count register sec fffff685h minute count register min r undefined
chapter 3 cpu function user?s manual u16237ej3v0ud 53 (5/6) manipulatable bits address function register name symbol r/w 1 8 16 32 default value fffff686h day/hour count register hourday fffff686h hour count register hour fffff687h day count register day r fffff688h week count register week fffff688h week count register l weekl fffff689h week count register h weekh undefined fffff68ah minute/second count setting register secminb 0000h fffff68ah second count setting register secb fffff68bh minute count setting register minb w 00h fffff68ch day/hour count setting register hourdayb 0000h fffff68ch hour count setting register hourb fffff68dh day count setting register dayb 00h fffff68eh week count setting register weekb 0000h fffff68eh week count setting register l weekbl fffff68fh week count setting register h weekbh 00h fffff6c0h oscillation stabilization time select register osts 04h fffff6c1h watchdog timer clock select register wdcs fffff6c2h watchdog timer mode register wdtm fffff802h system status register sys fffff820h power save mode register psmr 00h fffff828h processor clock control register pcc 03h fffff82ah wdt reset status register wdres undefined fffff840h correction address register 0 corad0 00000000h fffff840h correction address register 0l corad0l fffff842h correction address register 0h corad0h 0000h fffff844h correction address register 1 corad1 00000000h fffff844h correction address register 1l corad1l fffff846h correction address register 1h corad1h 0000h fffff848h correction address register 2 corad2 00000000h fffff848h correction address register 2l corad2l fffff84ah correction address register 2h corad2h 0000h fffff84ch correction address register 3 corad3 00000000h fffff84ch correction address register 3l corad3l fffff84eh correction address register 3h corad3h 0000h fffff880h correction control register corcn 00h fffffa00h asynchronous serial interface mode register 0 asim0 r/w 01h fffffa02h receive buffer register 0 rxb0 ffh fffffa03h asynchronous serial interface status register 0 asis0 r 00h fffffa04h transmit buffer register 0 txb0 r/w ffh fffffa05h asynchronous serial interface transmit status register 0 note asif0 r fffffa06h clock select register 0 cksr0 00h fffffa07h baud rate generator control register 0 brgc0 r/w ffh note although these registers can be manipulated in 8-bit units, it is recommended to manipulate them using a bit manipulation instruction.
chapter 3 cpu function user?s manual u16237ej3v0ud 54 (6/6) manipulatable bits address function register name symbol r/w 1 8 16 32 default value fffffa10h asynchronous serial interface mode register 1 asim1 r/w 01h fffffa12h receive buffer register 1 rxb1 ffh fffffa13h asynchronous serial interface status register 1 asis1 r 00h fffffa14h transmit buffer register 1 txb1 r/w ffh fffffa15h asynchronous serial interface transmit status register 1 note asif1 r fffffa16h clock select register 1 cksr1 00h fffffa17h baud rate generator compare register 1 brgc1 ffh fffffb00h pwm control register 0 pwmc0 40h fffffb02h pwm buffer register 0 pwmb0 0000h fffffb10h pwm control register 1 pwmc1 40h fffffb12h pwm buffer register 1 pwmb1 0000h fffffb20h pwm control register 2 pwmc2 40h fffffb22h pwm buffer register 2 pwmb2 0000h fffffb30h pwm control register 3 pwmc3 40h fffffb32h pwm buffer register 3 pwmb3 0000h fffffc00h external interrupt falling edge specification register 0 intf0 fffffc20h external interrupt rising edge specification register 0 intr0 fffffc40h pull-up resistor option register 0 pu0 fffffc42h pull-up resistor option register 1 pu1 fffffc44h pull-up resistor option register 2 pu2 fffffc46h pull-up resistor option register 3 pu3 fffffc48h pull-up resistor option register 4 pu4 r/w fffffd00h clocked serial inte rface mode register 0 csim0 fffffd01h clocked serial interfac e clock select register 0 csic0 fffffd02h serial i/o shift register 0 sio0 r fffffd03h reception-only serial i/o shift register 0 sioe0 fffffd04h clocked serial interface transmit buffer register 0 sotb0 fffffd10h clocked serial inte rface mode register 1 csim1 fffffd11h clocked serial interfac e clock select register 1 csic1 r/w fffffd12h serial i/o shift register 1 sio1 fffffd13h reception-only serial i/o shift register 1 sioe1 r 00h fffffd14h clocked serial interface transmit buffer register 1 sotb1 r/w note although these registers can be manipulated in 8-bit units, it is recommended to manipulate them using a bit manipulation instruction.
chapter 3 cpu function user?s manual u16237ej3v0ud 55 3.4.7 special registers special registers are registers that ar e protected from being written with illegal data due to a program hang-up. the v850es/pm1 has the following four special registers. ? power save control register (psc) ? processor clock control register (pcc) ? watchdog timer mode register (wdtm) ? wdt reset register (wdres) in addition, a command register (prcdm) is provided to pr otect against a write access to the special registers so that the applicat ion system does not inadvertently stop due to a program hang-up. a write access to the special registers is made in a specific sequence, and an illegal store operation is reported to the s ystem status register (sys).
chapter 3 cpu function user?s manual u16237ej3v0ud 56 (1) setting data to special registers set data to the special registers in the following sequence: <1> prepare data to be set to the special register in a general-purpose register. <2> write the data prepared in <1> to the prcmd register. <3> write the setting data to the special re gister (by using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) [example] with psc register st.b r11, psmr[r0] ; set psmr register. <1> mov 0x02, r10 <2> st.b r10, prcmd[r0] ; write prcmd register. <3> st.b r10, psc[r0] ; set psc register. <4> nop ; dummy instruction <5> nop ; dummy instruction <6> nop ; dummy instruction <7> nop ; dummy instruction <8> nop ; dummy instruction (next instruction) there is no special sequence to read a special register. cautions 1. when a store instruction is executed to store data in the command register, an interrupt is not acknowledged. this is because it is assumed that steps <2> and <3> above are performed by successive store instructions. if another instruction is placed between <2> and <3>, and if an interrupt is acknowledged by that instruction, the above sequence may not be established, causing malfunction. 2. although dummy data is written to th e prcmd register, use the same general-purpose register used to set the speci al register (<3> in example) to write data to the prcmd register (<2> in example). the same applies when a general-purpose register is used for addressing. 3. five nop instructions or more must be inserted immediately after setting the idle mode or software stop mode (by setting the psc.stp bit to 1).
chapter 3 cpu function user?s manual u16237ej3v0ud 57 (2) command register (prcmd) the prcmd register is an 8-bit regist er that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. the first write access to a special register (the pcc, psc, wd res, or wdtm register) is valid after data has been written in advance to the prcmd register. in this way, the value of the special register can be rewritten only in a specific sequence, so as to protect the register from an illegal write access. the prcmd register is write-only, in 8-bit units (undefined data is read when this register is read). the values are undefined after reset. 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch
chapter 3 cpu function user?s manual u16237ej3v0ud 58 (3) system status register (sys) status flags that indicate the opera tion status of the overall system are allocated to the sys register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 7 0 protection error did not occur. protection error occurred. prerr 0 1 detects protection error sys 6 0 5 0 4 0 3 0 2 0 1 0 <0> prerr after reset: 00h r/w address: fffff802h the prerr flag operates under the following conditions. (a) set condition (prerr flag = 1) (i) when data is written to a special register without writing anything to the prcmd register (when <3> is executed without executing <2> in 3.4.7 (1) setting data to special registers ) (ii) when data is written to a peri pheral i/o register other t han a special register (i ncluding execution of a bit manipulation instruction) after writi ng data to the prcmd register (if <3> in 3.4.7 (1) setting data to special registers is not the setting of a special register) remark even if a peripheral i/o register is read (excl uding execution of a bit ma nipulation in struction) between a write access to the prcmd register and a write access to a special register other than the wdtm register (pcc, psc, and wdres registers) (such as an access to the internal ram), the prerr flag is not set and data c an be written to the special register. (b) clear condition (prerr flag = 0) (i) when 0 is written to the sys.prerr flag (ii) when the system is reset cautions 1. if 0 is written to the prerr bit of the sys register, which is not a special register, immediately after a write access to the prcmd register, the prerr bit is cleared to 0 (the write access takes precedence). 2. if data is written to th e prcmd register, which is not a sp ecial register, immediately after a write access to the prcmd register , the prerr bit is set to 1.
chapter 3 cpu function user?s manual u16237ej3v0ud 59 3.4.8 cautions (1) system wait control register (vswc) be sure to set the vswc register first when using the v850es/pm1. after setting the vswc register, set the other registers as necessary. when using the external bus, perform the following initial settings after setting the above register. ? set each pin to the control mode by using the port-related registers. the vswc register controls wait of bus a ccess to the on-chip peripheral i/o registers. three clocks are required to access an on-chip peripheral i/o register (without a wa it cycle). the v850es/pm1 requires wait cycles according to the operating frequenc y. set the following value to the vswc register in accordance with the frequency used. the vswc register can be read or written in 8-bit units (address: fffff06eh, default value: 77h). operating frequency (f clk ) set value of vswc 2 mhz f clk 10 mhz 00h 10 mhz < f clk 20 mhz 02h
chapter 3 cpu function user?s manual u16237ej3v0ud 60 (2) access to special on-chip peripheral i/o registers the v850es/pm1 has two types of internal system buses. one is a cpu bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. because the clocks for the cpu bus and for the periphe ral bus are asynchronous, if a conflict between the access to the cpu and access to the peripheral hardware occurs, unexpected invalid data may be communicated. therefore, during an access to the pe ripheral hardware that may cause a conflict, the number of access cycles for the cpu is changed so that data can be communicated correctly. as a result, the cpu does not shift to the next instruction processing and the cpu processing is in the wait status. the number of clocks for instruction execution is therefore longer by the wait clocks shown below if this wait is generated. note this caution when real-time processing is required. during access to specific on-chip peripheral i/o register s, there are cases in which waits other than those set in the vswc register are required. the following shows the access method and how to calculate the number waits to be inserted (number of cpu clocks) in such cases. peripheral function register name access method k wdtm write 1 to 17 watchdog timer (wdt) {(16/f xx 2/((2 + m)/f cpu )} + 1 f xx : main clock frequency 16-bit timer/event counters 00 to 03 (tm00 to tm03) tmc00 to tmc03 read, modify, write 1 (fixed) a wait is generated during write tm10, tm11 read 1 and 2 cc100, cc101 cc110, cc111 read (in capture mode) write (in compare mode) 1 and 2 tmc100, tmc110 write 1 and 2 {(1/f xx 2/((2 + m)/f cpu )} + 1 in case the tmc1n0.tm1caen bit is set to 1 f xx : main clock frequency tmc100, tmc110 read, modify, write 1 to 3 16-bit timer/event counters (tm10, tm11) {(1/f xx 2/((2 + m)/f cpu )} + 1 f xx : main clock frequency pwmb0 to pwmb3 write 3 to 35 pwm {(1/f pwm /((2 + m)/f cpu )} + 1 while pwmcn is operating f pwm : clock frequency specified for pwm (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32) for details, see 13.3 (1) pwm control register n (pwmcn) . asynchronous serial interface (uart0, uart1) asis0, asis1 read 1 (fixed)
chapter 3 cpu function user?s manual u16237ej3v0ud 61 number of clocks increased by wait = (2 + m) k [clocks] (k: maximum number of waits) caution while the cpu is operating on the subclock and when a clock is not input to x1 or the main oscillator is stopped, do not access the regist ers that cause a wait (excluding the tmc00 to tmc03, asis0 and asis1 registers) using an access method that causes a wait. if a wait is generated, only a reset can release the wait. remark in the equation to calculate waits, the following applies. f cpu : cpu clock frequency m: set values of bits 2 to 0 of the vswc register f clk : internal system clock when f clk 10.0 mhz: m = 0 when f clk > 10.0 mhz: m = 2 if the product of the decimal places of the solution multiplied by (1/f cpu ) is equal to (1/f cpu )/(2 + m) or less, round off the decimal places, and if the product is more than (1/f cpu )/(2 + m), round up the decimal places.
chapter 3 cpu function user?s manual u16237ej3v0ud 62 (3) restriction on conflict between sld instruction and interrupt request (a) description if a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an in terrupt request before the instruction in <1> is complete, the execution result of the instru ction in <1> may not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sl d.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 ld.w [r11], r10 if the decode operation of the mov instruction immediately before the sld instruction and an interrupt reques t conflict before execution of the ld instruction is complete, the executi on result of instruction may not be stored in a register. mov r10, r28 sld.w 0x28, r10 (b) countermeasure <1> when compiler (ca850) is used use ca850 ver. 2.61 or later because generation of the corresponding instruction sequence can be automatically suppressed. <2> for assembler when executing the sld instruction immediately after instruction , avoid the above operation using either of the following methods. ? insert a nop instruction immediat ely before the sld instruction. ? do not use the same register as the sld instructi on destination register in the above instruction executed immediately befor e the sld instruction. . . .
user?s manual u16237ej3v0ud 63 chapter 4 port functions 4.1 features i/o ports: 68 pins can be set to input or output mode in 1-bit units. 4.2 basic configuration of port the v850es/pm1 has a total of 68 input/output port pins: por ts 0 to 4, 9, cm, cs, ct, dh, and dl. the port configuration is shown below. p00 p03 port 0 p90 p915 port 9 pcm0 pcm1 port cm pcs0 pcs2 port cs pct0 pct1 pct4 port ct pdh0 pdh2 port dh pdl0 pdl15 port dl p20 p21 port 2 p10 p14 port 1 p30 p36 port 3 p40 p46 port 4 table 4-1. i/o buffer power supply for each pin power supply corresponding pin av dd anin0, anin1 (n = 0 to 5) ev dd ports 0 to 4, 9, cm, cs, ct, dh, dl, reset
chapter 4 port functions user?s manual u16237ej3v0ud 64 4.3 port configuration table 4-2. port configuration item configuration control registers port n register (pn: n = 0 to 4, 9, cm, cs, ct, dh, dl) port n mode register (pmn: n = 0 to 4, 9, cm, cs, ct, dh, dl) port n mode control register (pmcn: n = 0 to 4, 9, cm, cs, ct, dh, dl) port n function control register (pfcn: n = 0, 1, 3, 4, 9) pull-up resistor option register n (pun: n = 0 to 4) ports i/o: 68 pins pull-up resistor software-controlled: 25 resistors (1) port n register (pn) data i/o with external devices is performed by writing to and reading from the pn regi ster. the pn register is configured by a port latch that reta ins the output data and a circuit that reads the status of pins. each bit of the pn register corresponds to one pin of por t n. the pn register can be read/written in 1-bit units. pn7 output 0. output 1. pnm 0 1 control of output data (in output mode) pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 1 2 3 7 5 6 7 pn after reset: 00h (output latch) r/w writing to/reading from the pn register is performed as follows regardless of the setting of the port n mode register (pmcn). table 4-3. writing to/reading from port n register (pn) setting in pmn register writing to pn register reading from pn register output mode (pmnm = 0) the value is written to the output latch note . in the port mode (pmcn = 0), the contents of the output latch are output from the pin. the value in the output latch is read. input mode (pmnm = 1) the value is written to the output latch. the status of the pin is not affected note . the status of the pin is read. note the value written to the output latch is retained until another value is written to the output latch.
chapter 4 port functions user?s manual u16237ej3v0ud 65 (2) port n mode register (pmn) the port n mode register specifies t he input mode/output mode of the port. each bit of the port pmn mode register corresponds to one pin of port n. the port n mode register can be specified in 1-bit units. pmn7 output mode input mode pmnm 0 1 controls i/o mode pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 pmn after reset: ffh r/w (3) port n mode control register (pmcn) the port n mode control register spec ifies the port mode/alternate function. each bit of the port pmcn mode control register corresponds to one pin of port n. the port n mode control register can be specified in 1-bit units. port mode alternate-function mode pmcnm 0 1 specifies of operation mode pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 pmcn after reset: 00h r/w
chapter 4 port functions user?s manual u16237ej3v0ud 66 (4) port n function control register (pfcn) the port n function control register specifies the alter nate function to be used when a pin has two or more alternate functions. each bit of the port pfcn function control register corre sponds to one pin of port n. the port n function control register can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcn after reset: 00h r/w alternate function 1 alternate function 2 pfcnm 0 1 specifies of alternate function (5) pull-up resistor option register n (pun) pull-up resistor option register n specifies the connection of an on-chip pull-up resistor. each bit of the pun register corresponds to one pin of port n. pull-up resistor option register n can be specified in 1-bit units. pun7 pun6 pun5 pun4 pun3 pun2 pun1 pun0 pun after reset: 00h r/w not connected connected punm 0 1 controls on-chip pull-up resistor connection
chapter 4 port functions user?s manual u16237ej3v0ud 67 (6) port setting set the ports as follows. figure 4-1. setting of each register and functions of pins pmcn register output mode input mode pmn register "0" "1" "0" "1" "0" "1" alternate function (when there are two alternate functions) port mode alternate function 1 alternate function 2 pfcn register remark follow the procedure below to switch to the alternate function. <1> set the pfcn register. <2> set the pmcn register. <3> set external interrupt rising/falling edge specification register n (intrn/intfn) (when setting the external interrupt pin). if the pmcn register is se t first, an unintended alternate function may be set while the pfcn register is being set.
chapter 4 port functions user?s manual u16237ej3v0ud 68 4.3.1 port 0 port 0 is a 4-bit i/o port that can be set to the input or output mode in 1-bit units. port 0 has an alternate function as the following pins. table 4-4. alternate-function pins of port 0 pin name alternate-function pin i/o pull note remark block type p00 nmi input a-3 p01 intp0 input a-3 p02 intp1 input a-3 port 0 p03 intp2/ti20 input provided ? a-5 note software pull-up function (1) registers (a) port 0 register (p0) 0 output 0. output 1. p0n 0 1 controls output data (in output mode) (n = 0 to 3) p0 0 0 0 p03 p02 p01 p00 after reset: 00h (output latch) r/w address: fffff400h (b) port 0 mode register (pm0) 1 output mode input mode pm0n 0 1 controls input/output mode (n = 0 to 3) pm0 1 1 1 pm03 pm02 pm01 pm00 after reset: ffh r/w address: fffff420h
chapter 4 port functions user?s manual u16237ej3v0ud 69 (c) port 0 mode control register (pmc0) 0 pmc0 0 0 0 pmc03 pmc02 pmc01 pmc00 i/o port intp2/ti20 input pmc03 0 1 specifies operation mode of p03 pin i/o port intp1 input pmc02 0 1 specifies operation mode of p02 pin i/o port intp0 input pmc01 0 1 specifies operation mode of p01 pin i/o port nmi input pmc00 0 1 specifies operation mode of p00 pin after reset: 00h r/w address: fffff440h (d) port 0 function control register (pfc0) 0 intp2 input ti20 input pfc03 0 1 specifies operation mode of p03 pin in control mode pfc0 0 0 0 pfc03 0 0 0 after reset: 00h r/w address: fffff460h caution when using port 0 to input an external inte rrupt, specify the valid edge of the interrupt request by using the intr0 and intf0 registers. when using the port for timer input, specify the valid edge of ti20 by using the tcl20 register. ? intr0: external interrupt rising ed ge specification regist er 0 (see 16.4.2 (1)) ? intf0: external interrupt falling edge specification register 0 (see 16.4.2 (1)) ? tcl20: timer clock select register 20 (see chapter 9 8-bit timer/event counters 20 and 21)
chapter 4 port functions user?s manual u16237ej3v0ud 70 (e) pull-up resistor option register 0 (pu0) 0 not connected connected pu0n 0 1 controls connection of on-chip pull-up resistor (n = 0 to 3) pu0 0 0 0 pu03 pu02 pu01 pu00 after reset: 00h r/w address: fffffc40h
chapter 4 port functions user?s manual u16237ej3v0ud 71 4.3.2 port 1 port 1 is a 5-bit i/o port that can be set to the input or output mode in 1-bit units. port 1 has an alternate function as the following pins. table 4-5. alternate-function pins of port 1 pin name alternate-function pin i/o pull note remark block type p10 pwm0 output b-3 p11 to00/pwm1 output b-4 p12 to01/pwm2 output b-4 p13 to20/pwm3 output b-4 port 1 p14 to21/ti21 i/o provided ? d-1 note software pull-up function (1) registers (a) port 1 register (p1) 0 output 0. output 1. p1n 0 1 controls output data (in output mode) (n = 0 to 4) p1 0 0 p14 p13 p12 p11 p10 after reset: 00h (output latch) r/w address: fffff402h (b) port 1 mode register (pm1) 1 output mode input mode pm1n 0 1 controls input/output mode (n = 0 to 4) pm1 1 1 pm14 pm13 pm12 pm11 pm10 after reset: ffh r/w address: fffff422h
chapter 4 port functions user?s manual u16237ej3v0ud 72 (c) port 1 mode control register (pmc1) 0 pmc1 0 0 pmc14 pmc13 pmc12 pmc11 pmc10 i/o port to21/ti21 i/o pmc14 0 1 specifies operation mode of p14 pin i/o port to20/pwm3 output pmc13 0 1 specifies operation mode of p13 pin i/o port to01/pwm2 output pmc12 0 1 specifies operation mode of p12 pin i/o port to00/pwm1 output pmc11 0 1 specifies operation mode of p11 pin i/o port pwm0 output pmc10 0 1 specifies operation mode of p10 pin after reset: 00h r/w address: fffff442h
chapter 4 port functions user?s manual u16237ej3v0ud 73 (d) port 1 function control register (pfc1) 0 pfc1 0 0 pfc14 pfc13 pfc12 pfc11 0 to21 output ti21 input pfc14 0 1 specifies operation mode of p14 pin in control mode to20 output pwm3 output pfc13 0 1 specifies operation mode of p13 pin in control mode to01 output pwm2 output pfc12 0 1 specifies operation mode of p12 pin in control mode to00 output pwm1 output pfc11 0 1 specifies operation mode of p11 pin in control mode after reset: 00h r/w address: fffff442h (e) pull-up resistor option register 1 (pu1) 0 not connected connected pu1n 0 1 controls connection of on-chip pull-up resistor (n = 0 to 4) pu1 0 0 pu14 pu13 pu12 pu11 pu10 after reset: 00h r/w address: fffffc42h
chapter 4 port functions user?s manual u16237ej3v0ud 74 4.3.3 port 2 port 2 is a 2-bit i/o port that can be set to the input or output mode in 1-bit units. port 2 has an alternate function as the following pins. table 4-6. alternate-function pins of port 2 pin name alternate-function pin i/o pull note remark block type p20 to02 output b-3 port 2 p21 to03 output provided ? b-3 note software pull-up function (1) registers (a) port 2 register (p2) 0 output 0. output 1. p2n 0 1 controls output data (in output mode) (n = 0, 1) p2 0 0 0 0 0 p21 p20 after reset: 00h (output latch) r/w address: fffff404h (b) port 2 mode register (pm2) 1 output mode input mode pm2n 0 1 controls input/output mode (n = 0, 1) pm2 1 1 1 1 1 pm21 pm20 after reset: ffh r/w address: fffff424h
chapter 4 port functions user?s manual u16237ej3v0ud 75 (c) port 2 mode control register (pmc2) 0 pmc2 0 0 0 0 0 pmc21 pmc20 i/o port to03 output pmc21 0 1 specifies operation mode of p21 pin i/o port to02 output pmc20 0 1 specifies operation mode of p20 pin after reset: 00h r/w address: fffff444h (d) pull-up resistor option register 2 (pu2) 0 not connected connected pu2n 0 1 controls connection of internal pull-up resistor (n = 0, 1) pu2 0 0 0 0 0 pu21 pu20 after reset: 00h r/w address: fffffc44h
chapter 4 port functions user?s manual u16237ej3v0ud 76 4.3.4 port 3 port 3 is a 7-bit i/o port that can be set to the input or output mode in 1-bit units. port 3 has an alternate function as the following pins. table 4-7. alternate-function pins of port 3 pin name alternate-function pin i/o pull note remark block type p30 rxd0 input a-6 p31 txd0 output b-3 p32 si1 input a-2 (without noise elimination) p33 so1 output b-3 p34 sck1 i/o c-2 p35 intp100/ti10/tclr10 input a-2 (with noise elimination) port 3 p36 intp110/ti11/tclr11 input provided ? a-2 (with noise elimination) note software pull-up function (1) registers (a) port 3 register (p3) 0 output 0. output 1. p3n 0 1 controls output data (in output mode) (n = 0 to 6) p3 p36 p35 p34 p33 p32 p31 p30 after reset: 00h (output latch) r/w address: fffff406h (b) port 3 mode register (pm3) 1 output mode input mode pm3n 0 1 controls input/output mode (n = 0 to 6) pm3 pm36 pm35 pm34 pm33 pm32 pm31 pm30 after reset: ffh r/w address: fffff426h
chapter 4 port functions user?s manual u16237ej3v0ud 77 (c) port 3 mode control register (pmc3) 0 pmc3 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 i/o port intp110/ti11/tclr11 input pmc36 0 1 specifies operation mode of p36 pin i/o port intp100/ti10/tclr10 input pmc35 0 1 specifies operation mode of p35 pin i/o port sck1 i/o pmc34 0 1 specifies operation mode of p34 pin i/o port so1 output pmc33 0 1 specifies operation mode of p33 pin after reset: 00h r/w address: fffff446h i/o port si1 input pmc32 0 1 specifies operation mode of p32 pin i/o port txd0 output pmc31 0 1 specifies operation mode of p31 pin i/o port rxd0 input pmc30 0 1 specifies operation mode of p30 pin caution when pmc35 and pmc36 bits = 1, perform the following setting: <1> to use intpn0: ? cmsn0 bit of tmcn1 register = 0, etin bit = 0, and eclrn bit = 0 ? setting of valid edge by sesn register <2> to use tin: ? cmsn0 bit of tmcn1 register = 1, etin bit = 1, and eclrn bit = 0 ? setting of valid edge by sesn register <3> to use tclrn: ? cmsn0 bit of tmcn1 register = 1, etin bit = 0, and eclrn bit = 1 ? setting of valid edge by sesn register
chapter 4 port functions user?s manual u16237ej3v0ud 78 (d) port 3 function control register (pfc3) pfc3 after reset: 00h r/w address: fffff466h 0 0 0 0 0 0 0 pfc30 rxd0 input reversed rxd0 input (reverses the value of the rxd0 pin and supplies it to uart0.) pfc30 0 1 specifies operation mode of p30 pin in control mode caution the pfc30 bit is valid only when the pmc30 bit = 1. (e) pull-up resistor option register 3 (pu3) 0 not connected. connected. pu3n 0 1 controls connection of internal pull-up resistor (n = 0 to 6) pu3 pu36 pu35 pu34 pu33 pu32 pu31 pu30 after reset: 00h r/w address: fffffc46h
chapter 4 port functions user?s manual u16237ej3v0ud 79 4.3.5 port 4 port 4 is a 7-bit i/o port that can be set to the input or output mode in 1-bit units. port 4 has an alternate function as the following pins. table 4-8. alternate-function pins of port 4 pin name alternate-function pin i/o pull note remark block type p40 si0 input a-2 (without noise elimination) p41 so0 output b-3 p42 sck0 i/o c-2 p43 rxd1 input a-6 p44 txd1 output b-3 p45 intp101/to10 i/o d-2 port 4 p46 intp111/to11 i/o provided ? d-2 note software pull-up function (1) registers (a) port 4 register (p4) 0 output 0. output 1. p4n 0 1 controls output data (in output mode) (n = 0 to 6) p4 p46 p45 p44 p43 p42 p41 p40 after reset: 00h (output latch) r/w address: fffff408h (b) port 4 mode register (pm4) 1 output mode input mode pm4n 0 1 controls input/output mode (n = 0 to 6) pm4 pm46 pm45 pm44 pm43 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h
chapter 4 port functions user?s manual u16237ej3v0ud 80 (c) port 4 mode control register (pmc4) 0 pmc4 pmc46 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 i/o port intp111/to11 i/o pmc46 0 1 specifies operation mode of p46 pin i/o port intp101/to10 i/o pmc45 0 1 specifies operation mode of p45 pin i/o port txd1 output pmc44 0 1 specifies operation mode of p44 pin i/o port rxd1 input pmc43 0 1 specifies operation mode of p43 pin after reset: 00h r/w address: fffff448h i/o port sck0 i/o pmc42 0 1 specifies operation mode of p42 pin i/o port so0 output pmc41 0 1 specifies operation mode of p41 pin i/o port si0 input pmc40 0 1 specifies operation mode of p40 pin
chapter 4 port functions user?s manual u16237ej3v0ud 81 (d) port 4 function control register (pfc4) pfc4 after reset: 00h r/w address: fffff468h 0 pfc46 pfc45 0 pfc43 0 0 0 intp111 input to11 output note pfc46 0 1 specifies operation mode of p46 pin in control mode intp101 input to10 output note pfc45 0 1 specifies operation mode of p45 pin in control mode rxd1 input reversed rxd1 input (reverses the value of the rxd1 pin and supplies it to uart1.) pfc43 0 1 specifies operation mode of p43 pin in control mode note setting of the pfc45 and pfc46 bits to 1 is enabled only when to1n output is enabled (tmc1n1.ento1n bit = 1) (n = 0, 1). otherwise, this setting is prohibited. caution the pfc4n bit is valid only when the pmc4n bit = 1 (n = 3, 5, or 6). (e) pull-up resistor option register 4 (pu4) 0 not connected. connected. pu4n 0 1 controls connection of internal pull-up resistor (n = 0 to 6) pu4 pu46 pu45 pu44 pu43 pu42 pu41 pu40 after reset: 00h r/w address: fffffc48h
chapter 4 port functions user?s manual u16237ej3v0ud 82 4.3.6 port 9 port 9 is a 16-bit i/o port that can be set to the input or output mode in 1-bit units. port 9 has an alternate function as the following pins. table 4-9. alternate-function pins of port 9 pin name alternate-function pin i/o pull note remark block type p90 a0 output b-2 p91 a1 output b-2 p92 a2 output b-2 p93 a3 output b-2 p94 a4 output b-2 p95 a5 output b-2 p96 a6 output b-2 p97 a7 output b-2 p98 a8/ti030 i/o a-4 p99 a9/ti031 i/o a-4 p910 a10/ti020 i/o a-4 p911 a11/ti021 i/o a-4 p912 a12/ti010 i/o a-4 p913 a13/ti011 i/o a-4 p914 a14/ti000 i/o a-4 port 9 p915 a15/ti001 i/o none ? a-4 note software pull-up function
chapter 4 port functions user?s manual u16237ej3v0ud 83 (1) registers (a) port 9 register (p9) p915 output 0. output 1. p9n 0 1 controls output data (in output mode) (n = 0 to 15) p9 p914 p913 p912 p911 p910 p99 p98 after reset: 0000h (output latch) r/w address: fffff412h, fffff413h p97 p96 p95 p94 p93 p92 p91 p90 8 9 10 11 12 13 14 15 remark the port 9 register (p9) can only be read or written in 16-bit units. if the higher 8 bits of the p9 register are used as p9h and the lower 8 bits as p9l, however, p9h and p9l can be manipulated in 8-bit or 1-bit units. (b) port 9 mode register (pm9) pm97 output mode input mode pm9n 0 1 controls input/output mode (n = 0 to 15) pm96 pm95 pm94 pm93 pm92 pm91 pm90 after reset: ffffh r/w address: fffff432h, fffff433h pm915 pm9 pm914 pm913 pm912 pm911 pm910 pm99 pm98 8 9 10 11 12 13 14 15 remark the pm9 register can only be read or written in 16-bit units. if the higher 8 bits of the pm9 register are used as pm9h and the lower 8 bits as pm9l, however, pm9h and pm9l can be manipulated in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u16237ej3v0ud 84 (c) port 9 mode control register (pmc9) (1/2) i/o port a15/ti001 i/o pmc915 0 1 specifies operation mode of p915 pin pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 after reset: note r/w address: fffff452h, fffff453h pmc915 pmc9 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 8 9 10 11 12 13 14 15 i/o port a14/ti000 i/o pmc914 0 1 specifies operation mode of p914 pin i/o port a11/ti021 i/o pmc911 0 1 specifies operation mode of p911 pin i/o port a10/ti020 i/o pmc910 0 1 specifies operation mode of p910 pin i/o port a9/ti031 i/o pmc99 0 1 specifies operation mode of p99 pin i/o port a8/ti030 i/o pmc98 0 1 specifies operation mode of p98 pin i/o port a13/ti011 i/o pmc913 0 1 specifies operation mode of p913 pin i/o port a12/ti010 i/o pmc912 0 1 specifies operation mode of p912 pin note in single-chip mode: 0000h in romless mode: ffffh remark the pmc9 register can only be read or written in 16-bit units. if the higher 8 bits of the pmc9 register are used as pmc9h and the lower 8 bits as pmc9l, however, pmc9h and pmc9l can be manipulated in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u16237ej3v0ud 85 (2/2) i/o port a7 output pmc97 0 1 specifies operation mode of p97 pin i/o port a6 output pmc96 0 1 specifies operation mode of p96 pin i/o port a5 output pmc95 0 1 specifies operation mode of p95 pin i/o port a4 output pmc94 0 1 specifies operation mode of p94 pin i/o port a3 output pmc93 0 1 specifies operation mode of p93 pin i/o port a2 output pmc92 0 1 specifies operation mode of p92 pin i/o port a1 output pmc91 0 1 specifies operation mode of p91 pin i/o port a0 output pmc90 0 1 specifies operation mode of p90 pin
chapter 4 port functions user?s manual u16237ej3v0ud 86 (d) port 9 function control register (pfc9) caution to perform address bus output (a0 to a 15), clear the pfc9 register to 0000h, and then set the pmc9 register to ffffh in 16-bit units. pfc9 a15 output ti001 input pfc915 0 1 specifies operation mode of p915 pin in control mode a14 output ti000 input pfc914 0 1 specifies operation mode of p914 pin in control mode a13 output ti011 input pfc913 0 1 specifies operation mode of p913 pin in control mode a12 output ti010 input pfc912 0 1 specifies operation mode of p912 pin in control mode after reset: 0000h r/w address: fffff472h, fffff473h 00 00 00 0 0 pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 8 9 10 11 12 13 14 15 a11 output ti021 input pfc911 0 1 specifies operation mode of p911 pin in control mode a10 output ti020 input pfc910 0 1 specifies operation mode of p910 pin in control mode a9 output ti031 input pfc99 0 1 specifies operation mode of p99 pin in control mode a8 output ti030 input pfc98 0 1 specifies operation mode of p98 pin in control mode remark the pfc9 register can only be read or written in 16-bit units. if the higher 8 bits of the pfc9 register are used as pfc9h and the lower 8 bits as pfc9l, however, pfc9h and pfc9l can be manipulated in 8-bit or 1-bit un its. however, this register is read-only if the pfc9l register is used in 1-bit units.
chapter 4 port functions user?s manual u16237ej3v0ud 87 4.3.7 port cm port cm is a 2-bit i/o port that can be set to the input or output mode in 1-bit units. port cm has an alternate function as the following pins. table 4-10. alternate-function pins of port cm pin name alternate-function pin i/o pull note remark block type pcm0 wait input a-1 port cm pcm1 clkout output none ? b-1 note software pull-up function (1) registers (a) port cm register (pcm) 0 output 0. output 1. pcmn 0 1 controls output data (in output mode) (n = 0, 1) pcm 0 0 0 0 0 pcm1 pcm0 after reset: 00h (output latch) r/w address: fffff00ch (b) port cm mode register (pmcm) 1 output mode input mode pmcmn 0 1 controls input/output mode (n = 0, 1) pmcm 1 11 1 1 pmcm1 pmcm0 after reset: ffh r/w address: fffff02ch
chapter 4 port functions user?s manual u16237ej3v0ud 88 (c) port cm mode control register (pmccm) 7 0 pmccm 6 0 5 0 4 0 3 0 2 0 1 pmccm1 0 pmccm0 i/o port clkout output pmccm1 0 1 specifies operation mode of pcm1 pin i/o port wait input pmccm0 0 1 specifies operation mode of pcm0 pin after reset: note r/w address: fffff04ch note in single-chip mode: 00h in romless mode: 01h
chapter 4 port functions user?s manual u16237ej3v0ud 89 4.3.8 port cs port cs is a 3-bit i/o port that can be set to the input or output mode in 1-bit units. port cs has an alternate function as the following pins. table 4-11. alternate-function pins of port cs pin name alternate-function pin i/o pull note remark block type pcs0 cs0 output b-1 pcs1 cs1 output b-1 port cs pcs2 cs2 output none ? b-1 note software pull-up function (1) registers (a) port cs register (pcs) 0 output 0. output 1. pcsn 0 1 controls output data (in output mode) (n = 0 to 2) pcs 0 0 0 0 pcs2 pcs1 pcs0 after reset: 00h (output latch) r/w address: fffff008h (b) port cs mode register (pmcs) 1 output mode input mode pmcsn 0 1 controls input/output mode (n = 0 to 2) pmcs 1 1 1 1 pmcs2 pmcs1 pmcs0 after reset: ffh r/w address: fffff028h
chapter 4 port functions user?s manual u16237ej3v0ud 90 (c) port cs mode control register (pmccs) 7 0 i/o port csn output pmccsn 0 1 specifies operation mode of pcsn pin (n = 0 to 2) pmccs 6 0 5 0 4 0 3 0 2 pmccs2 1 pmccs1 0 pmccs0 after reset: note r/w address: fffff048h note in single-chip mode: 00h in romless mode: 07h
chapter 4 port functions user?s manual u16237ej3v0ud 91 4.3.9 port ct port ct is a 3-bit i/o port that can be set to the input or output mode in 1-bit units. port ct has an alternate function as the following pins. table 4-12. alternate-function pins of port ct pin name alternate-function pin i/o pull note remark block type pct0 wr0 output b-1 pct1 wr1 output b-1 port ct pct4 rd output none ? b-1 note software pull-up function (1) registers (a) port ct register (pct) 0 output 0. output 1. pctn 0 1 controls output data (in output mode) (n = 0, 1, 4) pct 0 0 pct4 0 0 pct1 pct0 after reset: 00h (output) r/w address: fffff00ah (b) port ct mode register (pmct) 1 output mode input mode pmctn 0 1 controls input/output mode (n = 0, 1, 4) pmct 1 1 pmct4 1 1 pmct1 pmct0 after reset: ffh r/w address: fffff02ah
chapter 4 port functions user?s manual u16237ej3v0ud 92 (c) port ct mode control register (pmcct) 7 0 pmcct 6 0 5 0 4 pmcct4 3 0 2 0 1 pmcct1 0 pmcct0 i/o port rd output pmcct4 0 1 specifies operation mode of pct4 pin i/o port wr1 output pmcct1 0 1 specifies operation mode of pct1 pin i/o port wr0 output pmcct0 0 1 specifies operation mode of pct0 pin after reset: note r/w address: fffff04ah note in single-chip mode: 00h in romless mode: 13h
chapter 4 port functions user?s manual u16237ej3v0ud 93 4.3.10 port dh port dh is a 3-bit i/o port that can be set to the input or output mode in 1-bit units. port dh has an alternate function as the following pins. table 4-13. alternate-function pins of port dh pin name alternate-function pin i/o pull note remark block type pdh0 a16 output b-2 pdh1 a17 output b-2 port dh pdh2 a18 output none ? b-2 note software pull-up function (1) registers (a) port dh register (pdh) output 0. output 1. pdhn 0 1 controls output data (in output mode) (n = 0 to 2) pdh after reset: 00h (output latch) r/w address: fffff006h 7 0 6 0 5 0 4 0 3 0 2 pdh2 1 pdh1 0 pdh0 (b) port dh mode register (pmdh) 7 1 output mode input mode pmdhn 0 1 controls input/output mode (n = 0 to 2) 6 1 5 1 4 1 3 1 2 pmdh2 1 pmdh1 0 pmdh0 after reset: ffh r/w address: fffff026h pmdh
chapter 4 port functions user?s manual u16237ej3v0ud 94 (c) port dh mode control register (pmcdh) i/o port am output (address bus output) (m = 16 to 18) pmcdhn 0 1 specifies operation mode of pdhn pin (n = 0 to 2) 7 0 6 0 5 0 4 0 3 0 2 pmcdh2 1 pmcdh1 0 pmcdh0 after reset: note r/w address: fffff046h pmcdh note in single-chip mode: 00h in romless mode: 07h
chapter 4 port functions user?s manual u16237ej3v0ud 95 4.3.11 port dl port dl is a 16-bit i/o port that can be set to the input or output mode in 1-bit units. port dl has an alternate function as the following pins. table 4-14. alternate-function pins of port dl pin name alternate-function pin i/o pull note remark block type pdl0 d0 i/o c-1 pdl1 d1 i/o c-1 pdl2 d2 i/o c-1 pdl3 d3 i/o c-1 pdl4 d4 i/o c-1 pdl5 d5 i/o c-1 pdl6 d6 i/o c-1 pdl7 d7 i/o c-1 pdl8 d8 i/o c-1 pdl9 d9 i/o c-1 pdl10 d10 i/o c-1 pdl11 d11 i/o c-1 pdl12 d12 i/o c-1 pdl13 d13 i/o c-1 pdl14 d14 i/o c-1 port dl pdl15 d15 i/o none ? c-1 note software pull-up function
chapter 4 port functions user?s manual u16237ej3v0ud 96 (1) registers (a) port dl register (pdl) pdl15 output 0. output 1. pdln 0 1 controls output data (in output mode) (n = 0 to 15) pdl pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 after reset: 0000h (output latch) r/w address: fffff004h, fffff005h pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 8 9 10 11 12 13 14 15 remark the port dl register (pdl) can only be read or written in 16-bit units. if the higher 8 bits of the pdl register are us ed as pdlh, and the lower 8 bits as pdll, however, pdlh and pdll can be used as an 8-bit i/o port w hose input or output can be manipulated in 8-bit or 1-bit units. (b) port dl mode register (pmdl) pmdl7 output mode input mode pmdln 0 1 controls input/output mode (n = 0 to 15) pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 after reset: ffffh r/w address: ffff f024h, fffff025h pmdl15 pmdl pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 8 9 10 11 12 13 14 15 remark the pmdl register can only be read or written in 16-bit units. if the higher 8 bits of the pmdl register are used as pmdlh, and the lower 8 bits as pmdll, however, pmdlh and pmdll can be read or written in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u16237ej3v0ud 97 (c) port dl mode control register (pmcdl) i/o port dn i/o (data bus i/o) pmcdln 0 1 specifies operation mode of pdln pin (n = 0 to 15) 7 pmcdl7 6 pmcdl6 5 pmcdl5 4 pmcdl4 3 pmcdl3 2 pmcdl2 1 pmcdl1 0 pmcdl0 after reset: note r/w address: fffff044h, fffff045h pmcdl15 pmcdl pmcdl14pmcdl13 pmcdl12 pmcdl11pmcdl10 pmcdl9 pmcdl8 8 9 10 11 12 13 14 15 note in single-chip mode: 0000h in romless mode: ffffh caution do not specify d8 to d15 wh en the bs20 to bs00 bits of the bs c register = 0 (8-bit bus width). remark the pmcdl register can only be read or written in 16-bit units. if the higher 8 bits of the pmcdl register are used as pmcdlh, and the lower 8 bits as pmcdll, however, pmcdlh and pmcdll can be read or written in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u16237ej3v0ud 98 4.4 block diagram figure 4-2. block diagram of type a-1 wr pmc rd wr port pmn pmcmn wr pm pmmn selector selector internal bus output latch (pmn) address input signal in control mode
chapter 4 port functions user?s manual u16237ej3v0ud 99 figure 4-3. block diagram of type a-2 (1/2) (a) without noise elimination wr pmc rd wr port pmn pmcmn wr pu pumn wr pm pmmn ev dd p-ch selector selector internal bus output latch (pmn) address input signal in control mode
chapter 4 port functions user?s manual u16237ej3v0ud 100 figure 4-3. block diagram of type a-2 (2/2) (b) with noise elimination wr pmc rd wr port pmn pmcmn wr pu pumn wr pm pmmn ev dd p-ch selector selector internal bus output latch (pmn) address input signal in control mode noise elimination
chapter 4 port functions user?s manual u16237ej3v0ud 101 figure 4-4. block diagram of type a-3 wr pmc rd wr port pmn pmcmn wr intf intfmn wr pu pumn wr pm pmmn wr intr intrmn ev dd p-ch selector selector internal bus output latch (pmn) address noise elimination edge detection input signal in control mode
chapter 4 port functions user?s manual u16237ej3v0ud 102 figure 4-5. block diagram of type a-4 wr pmc rd wr port pmn pmcmn wr pm pmmn wr pfc pfcmn selector selector selector selector internal bus output latch (pmn) address output signal in control mode output buffer off signal input signal in control mode noise elimination
chapter 4 port functions user?s manual u16237ej3v0ud 103 figure 4-6. block diagram of type a-5 wr pmc rd wr port pmn pmcmn wr intf intfmn wr pu pumn wr pm pmmn wr intr intrmn wr pfc pfcmn ev dd p-ch selector selector selector internal bus output latch (pmn) address input signal 1 in control mode input signal 2 in control mode noise elimination edge detection noise elimination
chapter 4 port functions user?s manual u16237ej3v0ud 104 figure 4-7. block diagram of type a-6 wr pmc rd wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch selector selector selector internal bus output latch (pmn) address input signal in control mode
chapter 4 port functions user?s manual u16237ej3v0ud 105 figure 4-8. block diagram of type b-1 wr pmc rd address output signal in control mode wr port pmn pmcmn output latch (pmn) wr pm pmmn selector selector selector internal bus
chapter 4 port functions user?s manual u16237ej3v0ud 106 figure 4-9. block diagram of type b-2 wr pmc rd address output signal in control mode output buffer off signal wr port pmn pmcmn output latch (pmn) wr pm pmmn selector selector selector selector internal bus
chapter 4 port functions user?s manual u16237ej3v0ud 107 figure 4-10. block diagram of type b-3 wr pmc rd address output signal in control mode wr port pmn pmcmn output latch (pmn) wr pm pmmn wr pu pumn ev dd p-ch selector selector selector internal bus
chapter 4 port functions user?s manual u16237ej3v0ud 108 figure 4-11. block diagram of type b-4 wr pmc rd address output signal in control mode wr port pmn pmcmn output latch (pmn) wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch selector selector selector selector internal bus
chapter 4 port functions user?s manual u16237ej3v0ud 109 figure 4-12. block diagram of type c-1 wr pmc rd address output signal in control mode input enable signal in control mode input signal in control mode output enable signal in control mode output buffer off signal wr port pmn pmcmn output latch (pmn) wr pm pmmn selector selector selector selector internal bus
chapter 4 port functions user?s manual u16237ej3v0ud 110 figure 4-13. block diagram of type c-2 wr pmc wr port pmn pmcmn wr pu pumn wr pm pmmn ev dd p-ch rd selector selector selector internal bus output latch (pmn) address input signal in control mode output signal in control mode output enable signal in control mode
chapter 4 port functions user?s manual u16237ej3v0ud 111 figure 4-14. block diagram of type d-1 wr pmc rd wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch selector selector selector internal bus output latch (pmn) address output signal in control mode input signal in control mode noise elimination
chapter 4 port functions user?s manual u16237ej3v0ud 112 figure 4-15. block diagram of type d-2 wr pmc rd wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch selector selector selector internal bus output latch (pmn) address output signal in control mode input signal in control mode noise elimination
chapter 4 port functions user?s manual u16237ej3v0ud 113 4.5 register settings for ports when alternate function is used table 4-15 shows the register settings for the ports when each port pin is used as its alternate function pin. when using port pins as their alternate function pins, re fer to the descriptions of the respective functions.
chapter 4 port functions user?s manual u16237ej3v0ud 114 table 4-15. settings when port pins are used for alternate functions (1/5) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcnx bit of pfcn register other bits (registers) intr00 (intr0), intf00 (intf0) intr01 (intr0), intf01 (intf0) intr02 (intr0), intf02 (intf0) intr03 (intr0), intf03 (intf0) tcl202 to tcl200 (tcl20) tcl212 to tcl210 (tcl21) ? ? ? ? ? ? ? ? ? ? input input input input input output output output output output output output output input output output p00 p01 p02 p03 p10 p11 p12 p13 p14 p20 p21 nmi intp0 intp1 intp2 ti20 pwm0 to00 pwm1 to01 pwm2 to20 pwm3 to21 ti21 to02 to03 p00 = setting not required p01 = setting not required p02 = setting not required p03 = setting not required p03 = setting not required p10 = setting not required p11 = setting not required p11 = setting not required p12 = setting not required p12 = setting not required p13 = setting not required p13 = setting not required p14 = setting not required p14 = setting not required p20 = setting not required p21 = setting not required pm00 = setting not required pm01 = setting not required pm02 = setting not required pm03 = setting not required pm03 = setting not required pm10 = setting not required pm11 = setting not required pm11 = setting not required pm12 = setting not required pm12 = setting not required pm13 = setting not required pm13 = setting not required pm14 = setting not required pm14 = setting not required pm20 = setting not required pm21 = setting not required pmc00 = 1 pmc01 = 1 pmc 02 = 1 pmc03 = 1 pmc03 = 1 pmc10 = 1 pmc11 = 1 pmc11 = 1 pmc12 = 1 pmc12 = 1 pmc13 = 1 pmc13 = 1 pmc14 = 1 pmc14 = 1 pmc20 = 1 pmc21 = 1 pfc03 = 0 pfc03 = 1 pfc11 = 0 pfc11 = 1 pfc12 = 0 pfc12 = 1 pfc13 = 0 pfc13 = 1 pfc14 = 0 pfc14 = 1 ? ? ? ? ? ?
chapter 4 port functions user?s manual u16237ej3v0ud 115 table 4-15. settings when port pins are used for alternate functions (2/5) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcnx bit of pfcn register other bits (registers) set the valid edge by using the ses10 register set the valid edge by using the ses11 register set the valid edge by using the ses10 register set the valid edge by using the ses11 register input input output input output i/o input input input input input input input output i/o input input output input output input output p30 p31 p32 p33 p34 p35 p36 p40 p41 p42 p43 p44 p45 p46 rxd0 rxd0 txd0 si1 so1 sck1 intp100 ti10 tclr10 intp110 ti11 tclr11 si0 so0 sck0 rxd1 rxd1 txd1 intp101 to10 intp111 to11 p30 = setting not required p30 = setting not required p31 = setting not required p32 = setting not required p33 = setting not required p34 = setting not required p35 = setting not required p35 = setting not required p35 = setting not required p36 = setting not required p36 = setting not required p36 = setting not required p40 = setting not required p41 = setting not required p42 = setting not required p43 = setting not required p43 = setting not required p44 = setting not required p45 = setting not required p45 = setting not required p46 = setting not required p46 = setting not required pm30 = setting not required pm30 = setting not required pm31 = setting not required pm32 = setting not required pm33 = setting not required pm34 = setting not required pm35 = setting not required pm35 = setting not required pm35 = setting not required pm36 = setting not required pm36 = setting not required pm36 = setting not required pm40 = setting not required pm41 = setting not required pm42 = setting not required pm43 = setting not required pm43 = setting not required pm44 = setting not required pm45 = setting not required pm45 = setting not required pm46 = setting not required pm46 = setting not required pmc30 = 1 pmc30 = 1 pmc31 = 1 pmc32 = 1 pmc33 = 1 pmc34 = 1 pmc35 = 1 pmc35 = 1 pmc35 = 1 pmc36 = 1 pmc36 = 1 pmc36 = 1 pmc40 = 1 pmc41 = 1 pmc42 = 1 pmc43 = 1 pmc43 = 1 pmc44 = 1 pmc45 = 1 pmc45 = 1 pmc46 = 1 pmc46 = 1 pfc30 = 0 pfc30 = 1 pfc43 = 0 pfc43 = 1 pfc45 = 0 pfc45 = 1 pfc46 = 0 pfc46 = 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 4 port functions user?s manual u16237ej3v0ud 116 table 4-15. settings when port pins are used for alternate functions (3/5) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcnx bit of pfcn register other bits (registers) note note note note note note note note note note note note note note note note ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? output output output output output output output output output input output input output input output input output input output input output input output input p90 p91 p92 p93 p94 p95 p96 p97 p98 p99 p910 p911 p912 p913 p914 p915 a0 a1 a2 a3 a4 a5 a6 a7 a8 ti030 a9 ti031 a10 ti020 a11 ti021 a12 ti010 a13 ti011 a14 ti000 a15 ti001 p90 = setting not required p91 = setting not required p92 = setting not required p93 = setting not required p94 = setting not required p95 = setting not required p96 = setting not required p97 = setting not required p98 = setting not required p98 = setting not required p99 = setting not required p99 = setting not required p910 = setting not required p910 = setting not required p911 = setting not required p911 = setting not required p912 = setting not required p912 = setting not required p913 = setting not required p913 = setting not required p914 = setting not required p914 = setting not required p915 = setting not required p915 = setting not required pm90 = setting not required pm91 = setting not required pm92 = setting not required pm93 = setting not required pm94 = setting not required pm95 = setting not required pm96 = setting not required pm97 = setting not required pm98 = setting not required pm98 = setting not required pm99 = setting not required pm99 = setting not required pm910 = setting not required pm910 = setting not required pm911 = setting not required pm911 = setting not required pm912 = setting not required pm912 = setting not required pm913 = setting not required pm913 = setting not required pm914 = setting not required pm914 = setting not required pm915 = setting not required pm915 = setting not required pmc90 = 1 pmc91 = 1 pmc92 = 1 pmc93 = 1 pmc94 = 1 pmc95 = 1 pmc96 = 1 pmc97 = 1 pmc98 = 1 pmc98 = 1 pmc99 = 1 pmc99 = 1 pmc910 = 1 pmc910 = 1 pmc911 = 1 pmc911 = 1 pmc912 = 1 pmc912 = 1 pmc913 = 1 pmc913 = 1 pmc914 = 1 pmc914 = 1 pmc915 = 1 pmc915 = 1 pfc98 = 0 pfc98 = 1 pfc99 = 0 pfc99 = 1 pfc910 = 0 pfc910 = 1 pfc911 = 0 pfc911 = 1 pfc912 = 0 pfc912 = 1 pfc913 = 0 pfc913 = 1 pfc914 = 0 pfc914 = 1 pfc915 = 0 pfc915 = 1 note to set the a0 to a15 pins, clear the pfc9 register to 0000h and set the pmc9 register to ffffh in 16-bit units.
chapter 4 port functions user?s manual u16237ej3v0ud 117 table 4-15. settings when port pins are used for alternate functions (4/5) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? input output output output output output output output output output output pcm0 pcm1 pcs0 pcs1 pcs2 pct0 pct1 pct4 pdh0 pdh1 pdh2 wait clkout cs0 cs1 cs2 wr0 wr1 rd a16 a17 a18 pcm0 = setting not required pcm1 = setting not required pcs0 = setting not required pcs1 = setting not required pcs2 = setting not required pct0 = setting not required pct1 = setting not required pct4 = setting not required pdh0 = setting not required pdh1 = setting not required pdh2 = setting not required pmcm0 = setting not required pmcm1 = setting not required pmcs0 = setting not required pmcs1 = setting not required pmcs2 = setting not required pmct0 = setting not required pmct1 = setting not required pmct4 = setting not required pmdh0 = setting not required pmdh1 = setting not required pmdh2 = setting not required pmccm0 = 1 pmccm1 = 1 pmccs 0 = 1 pmccs1 = 1 pmccs2 = 1 pmcct0 = 1 pmcct1 = 1 pmcct4 = 1 pmcdh0 = 1 pmcdh1 = 1 pmcdh2 = 1 ? ? ? ? ? ? ? ? ? ? ?
chapter 4 port functions user?s manual u16237ej3v0ud 118 table 4-15. settings when port pins are used for alternate functions (5/5) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o pdl0 pdl1 pdl2 pdl3 pdl4 pdl5 pdl6 pdl7 pdl8 pdl9 pdl10 pdl11 pdl12 pdl13 pdl14 pdl15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 pdl0 = setting not required pdl1 = setting not required pdl2 = setting not required pdl3 = setting not required pdl4 = setting not required pdl5 = setting not required pdl6 = setting not required pdl7 = setting not required pdl8 = setting not required pdl9 = setting not required pdl10 = setting not required pdl11 = setting not required pdl12 = setting not required pdl13 = setting not required pdl14 = setting not required pdl15 = setting not required pmdl0 = setting not required pmdl1 = setting not required pmdl2 = setting not required pmdl3 = setting not required pmdl4 = setting not required pmdl5 = setting not required pmdl6 = setting not required pmdl7 = setting not required pmdl8 = setting not required pmdl9 = setting not required pmdl10 = setting not required pmdl11 = setting not required pmdl12 = setting not required pmdl13 = setting not required pmdl14 = setting not required pmdl15 = setting not required pmcdl0 = 1 pmcdl1 = 1 pmcdl2 = 1 pmcdl3 = 1 pmcdl4 = 1 pmcdl5 = 1 pmcdl6 = 1 pmcdl7 = 1 pmcdl8 = 1 pmcdl9 = 1 pmcdl10 = 1 pmcdl11 = 1 pmcdl12 = 1 pmcdl13 = 1 pmcdl14 = 1 pmcdl15 = 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 4 port functions user?s manual u16237ej3v0ud 119 4.6 cautions 4.6.1 cautions on bit manipulation instruction for port n register (pn) when 1-bit manipulation instruction is executed to a port t hat includes both input and out put pins, the value of the output latch of the input port not subjec t to the manipulation may be rewritten. therefore, it is recommended to rewrite the value of t he output latch before switching a port from input mode to output mode. when p90 is an output port, p91 to p97 are inpu t ports (the status of all pi ns is high level), and the value of the port latch is 00h, if the output of output port 90 is changed from low level to high level by a bit manipulation instruction, t he value of the port latch is ffh. explanation: the contents written to/read from the pn register of a port whose pmnm bit is 1 are the output latch contents/pin status. bit manipulation instructions are executed in the following order in the v850es/pm1. <1> the pn register is read in 8-bit units. <2> the targeted bit is manipulated. <3> the pn register is written in 8-bit units. in <1> above, p90, an output port, reads the value of the output latch (0), while p91 to p97, input ports, read the statuses of pins. if the status of the pins p91 to p97 is high level at this time, the read value is feh. in <2> above, the value is ffh. in <3> above, ffh is written to the output latch. figure 4-16. bit manipulation instruction (p90) low level is output the bit manipulation instruction (set1 0, p9l[r0]) is executed to p90. status of pins: high level low level is output status of pins: high level p90 p91 to p97 port 9l latch port 9l latch 00000000 p90 p91 to p97 11111111 bit manipulation instruction <1> the p9l register is read in 8-bit units. ? when p90, which is an output port, is read, the value of the port latch (0) is read. ? when p91 to p97, which are input ports, are read, the status of the pins (1) is read. <2> bit 0 (the p90 bit) is set to 1. <3> the results of <2> above are written to the output latch of the p9l register in 8-bit units.
user?s manual u16237ej3v0ud 120 chapter 5 bus control function the v850es/pm1 is provided with an external bus interfac e function by which external memories such as rom and ram, and i/o c an be connected. 5.1 features separate bus output with a minimum of 2 bus cycles three-space chip select function 8-bit/16-bit data bus selectable (for each area selected by chip select function) wait function ? programmable wait function of up to 7 states (selec table for each area selected by chip select function) ? external wait function using wait pin idle state function
chapter 5 bus control function user?s manual u16237ej3v0ud 121 5.2 bus control pins the pins used to connect an external device are listed in the table below. table 5-1. bus control pins bus control pin alternate-function pin i/o function d0 to d15 pdl0 to pdl15 i/o data bus a0 to a15 p90 to p915 output address bus a16 to a18 pdh0 to pdh2 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock cs0 to cs2 pcs0 to pcs2 output chip select wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal 5.2.1 pin status when internal rom, intern al ram, or on-chip peripheral i/o is accessed when the internal rom, internal ram, or on-chip peripheral i/o is accessed, the statuses of the pins are as follows. table 5-2. pin status when internal rom, in ternal ram, or on-chip peripheral i/o is accessed address bus (a18 to a0) undefined note data bus (d15 to d0) hi-z control signal inactive note the output data varies depending on the area to be accessed. when the internal rom area or internal ram area is accessed, the output value may different between the v850es/pm1 and ie. caution when a write access to the internal rom area is made, the ad dress, data, and control signals are activated in the same way as the acce ss to the external memory area. 5.2.2 pin status in each operation mode for the pin status of the v850es/pm1 in each operation mode, see 2.2 pin status .
chapter 5 bus control function user?s manual u16237ej3v0ud 122 5.3 memory block function the 64 mb memory space is divided into memory blocks of (lower) 2 mb, 2 mb, and 4 mb. the programmable wait function and bus cycl e operation mode for each of these blocks can be independently controlled in one-block units. figure 5-1. data memory map: physical addresses (80 kb) use prohibited internal rom area note 2 (1 mb) external memory area note 1 (1 mb) internal ram area (10 kb) on-chip peripheral i/o area (4 kb) use prohibited external memory area note 1 (4 mb) external memory area note 1 (2 mb) (2 mb) cs0 cs1 cs2 3ffffffh 3fec000h 3febfffh 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h 3ffffffh 3fff000h 3ffefffh 3ffc800h 3ffc7ffh 3fec000h 01fffffh 0100000h 00fffffh 0000000h notes 1. each of these areas is a 512 kb space of 0100000h to 017ffffh, 02000 00h to 027ffffh, or 0400000h to 047ffffh (01800 00h to 01fffffh, 0280000h to 03fffffh, and 0480000h to 07fffffh are an image). 2. this area is an external memory area in the case of a data write access.
chapter 5 bus control function user?s manual u16237ej3v0ud 123 5.3.1 chip select control function of the 64 mb (linear) address space, the lower 8 mb ( 0000000h to 0ffffffh) in clude three chip select functions, cs0 to cs2. the areas that can be selected by cs0 to cs2 are fixed. by using these chip select functions, the memory block can be divided to enable effective use of the memory space. the allocation of the memory blocks is shown in the table below. v850es/pm1 (single-chip mode) v850es/pm1 (romless mode) cs0 0100000h to 017ffffh (512 kb) 0000000h to 007ffffh (512 kb) cs1 0200000h to 027ffffh (512 kb) 0200000h to 027ffffh (512 kb) cs2 0400000h to 047ffffh (512 kb) 0400000h to 047ffffh (512 kb)
chapter 5 bus control function user?s manual u16237ej3v0ud 124 5.4 bus access 5.4.1 number of clocks for access the following table shows the number of basic clocks required for accessing each resource. area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) external memory (16 bits) instruction fetch (normal access) 1 1 note 1 2 + n note 2 instruction fetch (branch) 2 2 note 2 2 + n note 2 operand data access 3 1 2 + n note 2 notes 1. when the access conflicts with a data access, the cycle is incremented by 1. 2. n: number of wait states remark unit: clocks/access 5.4.2 bus size setting function the bus size of each external memory area selected by csn can be set (to 8 bits or 16 bits) by using the bsc register. the external memory area is selected by cs0 to cs2. (1) bus size configuration register (bsc) the bsc register can be read or written in 16-bit units. reset sets this register to 5555h. caution write to the bsc register after reset, an d then do not change the set values. also, do not access an external memory area until the initial se ttings of the bsc register are complete. after reset: 5555h r/w address: fffff066h 0 0 bsn0 0 1 8 bits 16 bits bsc 1 1 0 0 1 bs20 0 0 1 bs10 0 0 1 bs00 8 9 10 11 12 13 data bus width of csn space (n = 0 to 2) 14 15 1 2 3 4 5 6 7 0 cs0 csn signal cs2 cs1 caution be sure to set bits 14, 12, 10, 8, and 6 to ?1?, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to ?0?.
chapter 5 bus control function user?s manual u16237ej3v0ud 125 5.4.3 access by bus size the v850es/pm1 accesses the peripheral i/o and external memory in 8-bit, 16-bit, or 32-bit units. the bus size is as follows. ? the bus size of the peripheral i/o is fixed to 16 bits. ? the bus size of the external memory is selectable from 8 bits or 16 bits (by using the bsc register). the operation when each of the above is accessed is descr ibed below. all data is accessed starting from the lower side. the v850es/pm1 supports only the little endian format. figure 5-2. little endian address in word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 (1) data space the v850es/pm1 has an address misalign function. with this function, data can be placed at all addresse s, regardless of the format of the data (word data or halfword data). however, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (a) halfword-length data access a byte-length bus cycle is generated twice if t he least significant bit of the address is 1. (b) word-length data access (i) a byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (ii) a halfword-length bus cycle is generated twic e if the lower 2 bits of the address are 10.
chapter 5 bus control function user?s manual u16237ej3v0ud 126 (2) byte access (8 bits) (a) 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 15 8 2n + 1 address byte data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus
chapter 5 bus control function user?s manual u16237ej3v0ud 127 (3) halfword access (16 bits) (a) 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 15 8 2n address 15 8 2n + 1 halfword data external data bus first access second access 7 0 7 0 15 8 15 8 7 0 7 0 15 8 15 8 2n + 2 halfword data external data bus 2n address halfword data external data bus address 2n + 1 (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access 7 0 7 0 15 8 address 7 0 7 0 15 8 2n + 1 address 2n halfword data external data bus halfword data external data bus first access second access 7 0 7 0 15 8 7 0 7 0 15 8 2n + 2 2n + 1 address address halfword data external data bus halfword data external data bus
chapter 5 bus control function user?s manual u16237ej3v0ud 128 (4) word access (32 bits) (a) 16-bit data bus width (1/2) <1> access to address (4n) first access second access 7 0 7 0 15 8 4n 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function user?s manual u16237ej3v0ud 129 (a) 16-bit data bus width (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 word data external data bus address word data external data bus address <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function user?s manual u16237ej3v0ud 130 (b) 8-bit data bus width (1/2) <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 1 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function user?s manual u16237ej3v0ud 131 (b) 8-bit data bus width (2/2) <3> access to address (4n + 2) first access second access third access fourth access word data external data bus address word data external data bus address word data external data bus address word data external data bus address 7 0 7 0 15 8 4n + 2 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function user?s manual u16237ej3v0ud 132 5.5 wait function 5.5.1 programmable wait function (1) data wait control register 0 (dwc0) to realize interfacing with a low-speed memory or i/o, up to seven data wait states can be inserted in the bus cycle that is executed for each cs space. the number of wait states can be pr ogrammed by using the dwc0 register . immediately after system reset, 7 data wait states are inserted for all the blocks. the dwc0 register can be read or written in 16-bit units. reset sets this register to 7777h. cautions 1. the internal rom and internal ram areas are not subject to programmable wait, and are always accessed without a wait state. the on-ch ip peripheral i/o area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. write to the dwc0 register after reset, a nd then do not change the set values. also, do not access an external memory area until the in itial settings of the dwc0 register are complete. after reset: 7777h r/w address: fffff484h 0 0 dwn2 0 0 0 0 1 1 1 1 dwn1 0 0 1 1 0 0 1 1 dwn0 0 1 0 1 0 1 0 1 none 1 2 3 4 5 6 7 dwc0 1 dw12 1 dw11 1 dw10 0 0 dw22 dw02 dw21 dw01 dw20 dw00 8 9 10 11 12 13 number of wait states inserted in csn space (n = 0 to 2) 14 15 1 2 3 4 5 6 7 0 cs0 csn signal csn signal cs2 cs1 caution be sure to set bits 14, 13, and 12 to ?1?, and clear bits 15, 11, 7, and 3 to ?0?.
chapter 5 bus control function user?s manual u16237ej3v0ud 133 5.5.2 external wait function to synchronize an extremely slow external memory, i/o, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (wait). access to each area of the internal rom, internal ram, a nd on-chip peripheral i/o is not subject to control by the external wait function, in the same man ner as the programmable wait function. the wait signal can be input asynchronously to clko ut, and is sampled at the rising edge of the clock immediately after the t1 and tw states of the bus cycle. if the setup/hold time of the sa mpling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all. 5.5.3 relationship between programm able wait and external wait wait cycles are inserted as the result of an or operation between the wait cycles specifi ed by the set value of the programmable wait and the wait cycles controlled by the wait pin. wait control programmable wait wait via wait pin for example, if the timing of the programmable wait an d the wait pin signal is as illustrated below, three wait states will be inserted in the bus cycle. figure 5-3. example of inserting wait states t1 tw tw tw t2 clkout wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing.
chapter 5 bus control function user?s manual u16237ej3v0ud 134 5.5.4 programmable address wait function address-setup or address-hold waits to be inserted in each bus cycle can be set by using the awc register. address wait insertion is set for each chip select area (cs0 to cs2). if an address setup wait is inserted, it seems that the high-clock period of t1 state is extended by 1 clock. if an address hold wait is inserted, it seems that the low- clock period of t1 state is extended by 1 clock. (1) address wait control register (awc) the awc register can be read or written in 16-bit units. reset sets this register to ffffh. cautions 1. the internal rom, in ternal ram, and on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the awc register after reset, and then do not charge the set values. also, do not access an external memory area until the initial settings of the awc register are complete. after reset: ffffh r/w address: fffff488h 1 1 ahwn 0 1 not inserted inserted awc 1 1 1 ahw2 1 asw2 1 ahw1 1 asw1 1 ahw0 1 asw0 8 9 10 11 12 13 specifies insertion of address hold wait (n = 0 to 2) 14 15 1 2 3 4 5 6 7 0 aswn 0 1 not inserted inserted specifies insertion of address setup wait (n = 0 to 2) cs0 csn signal cs2 cs1 caution be sure to set bits 15 to 6 to ?1?.
chapter 5 bus control function user?s manual u16237ej3v0ud 135 5.6 idle state insertion function to facilitate interfacing with low-speed memories, one idle state (ti) can be inserted a fter the t2 state in the bus cycle that is executed for each space se lected by the memory block function. by inserting an idle state, the data output float delay time of the memory can be secured du ring read access (an idle state cannot be inserted during write access). whether the idle state is to be inserted c an be programmed by using the bcc register. an idle state is inserted for all t he areas immediately after system reset. (1) bus cycle control register (bcc) the bcc register can be read or written in 16-bit units. reset sets this register to aaaah. cautions 1. the internal rom, internal ram, a nd on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the bcc register are complete. after reset: aaaah r/w address: fffff48ah 1 1 bcn1 0 1 not inserted i nserted bcc 0 0 1 bc21 0 0 1 bc11 0 0 1 bc01 0 0 8 9 10 11 12 13 specifies insertion of idle state (n = 0 to 2) 14 15 1 2 3 4 5 6 7 0 cs0 csn signal cs2 cs1 caution be sure to set bits 15, 13, 11, 9, and 7 to ?1?, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to ?0?.
chapter 5 bus control function user?s manual u16237ej3v0ud 136 5.7 bus priority instruction fetch (branch), instruction fetch (successive), and operand data accesses are executed in the external bus cycle. operand data access has the highest priority, followed by instruction fetch (branch) and instruction fetch (successive). an instruction fetch may be inserted between the read access and write access in a read-modify-write access. if an instruction is executed for two or more accesses, an instruction fetch is not inserted between accesses due to bus size limitations. table 5-3. bus priority priority external bus cycle bus master operand data access cpu instruction fetch (branch) cpu high low instruction fetch (successive) cpu
chapter 5 bus control function user?s manual u16237ej3v0ud 137 5.8 bus timing figure 5-4. bus read timing (b us size: 16 bits, 16-bit access) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout note a0 to a18 cs0 to cs2 wait d0 to d15 rd 8-bit access d15 to d8 d7 to d0 odd address active hi-z even address active hi-z note clkout is not output in the romless mode immediately after reset has been released. it is output in the control mode (pmccm). figure 5-5. bus read timing (bus size: 8 bits) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a0 to a18 cs0 to cs2 wait d0 to d7 rd
chapter 5 bus control function user?s manual u16237ej3v0ud 138 figure 5-6. bus write timing (bus size: 16 bits, 16-bit access) t1 a1 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a0 to a18 cs0 to cs2 wait d0 to d15 wr0, wr1 8-bit access d15 to d8 d7 to d0 odd address active undefined even address active undefined figure 5-7. bus write timing (bus size: 8 bits) t1 a1 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 10 clkout a0 to a18 cs0 to cs2 wait d0 to d7 wr0, wr1 10 10
chapter 5 bus control function user?s manual u16237ej3v0ud 139 figure 5-8. address wait timing (bus read, bus size: 16 bits, 16-bit access) (a) without wait inserted (b) with wait inserted tasw t1 tahw t2 clkout a0 to a18 cs0 to cs2 wait d0 to d15 rd d1 a1 t1 t2 clkout a0 to a18 cs0 to cs2 wait d0 to d15 rd d1 a1 remarks 1. tasw (address setup wait): image of extended high-level width of t1 state 2. tahw (address hold wait): image of ex tended low-level width of t1 state
user?s manual u16237ej3v0ud 140 chapter 6 clock generation function 6.1 overview the features of the clock generat ion function are as follows. main clock oscillator ? f x = 2 to 20 mhz (at 2.7 to 3.6 v operation) subclock oscillator ? f xt = 32.768 khz (at 2.2 to 3.6 v operation) generation of internal system clock and cpu clock ? five steps (f xx , f xx /2, f xx /4, f xx /8, f xt ) generation of peripheral clock clock output function remark f x : main clock oscillation frequency f xx : main clock frequency
chapter 6 clock generation function user?s manual u16237ej3v0ud 141 6.2 configuration figure 6-1. clock generator frc bit mfrc bit ck3, ck1, ck0 bits stop mode cls, mck bits subclock oscillator port cm wdt clock control prescaler 1 prescaler 2 idle control idle control halt control halt mode cls bit cpu clock rtc clock peripheral clock wdt clock internal system clock main clock oscillator main clock oscillator stop control subclock oscillator stop control xt1 xt2 stop mode cls bit clkout x1 x2 idle selector f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xt f xx to f xx /2,048 f xt f xt f x f xx f xw remark f x : main clock oscillation frequency f xx : main clock frequency f clk : internal system clock frequency f xt : subclock frequency f cpu : cpu clock frequency f xw : watchdog timer clock frequency
chapter 6 clock generation function user?s manual u16237ej3v0ud 142 (1) main clock oscillator this circuit oscillates the following frequency (f x ): ? 2 to 20 mhz (at 2.7 to 3.6 v operation) (2) subclock oscillator this circuit oscillates a frequency of 32.768 khz (f xt ). (3) main clock resonator stop control this circuit generates a control signal that st ops oscillation of the main clock resonator. if the software stop mode is set when the cls bit of the pr ocessor clock control register (pcc) is 0, or if the mck bit of the pcc register is set to 1 when the cls bit is 1, oscillation of the main clock resonator is stopped. (4) subclock resonator stop control this circuit generates a control signal that st ops oscillation of the subclock resonator. if the software stop mode is set when the cls bit is 1, oscillation of the subclock resonator is stopped. (5) prescaler 1 this circuit generates the clock (f xx to f xx /2,048) to be supplied to the on-chip peripheral functions. the clock is supplied to the following blocks: tm00 to tm03, tm10, tm11, tm20, tm21, csi0, csi1, uart0, uart1, pwm0 to pwm3, adc (6) prescaler 2 this circuit divides the main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /8) is supplied to the selector that generates the internal system clock (f clk ). f clk is the clock that is supplied to the cpu, intc , and rom correction blocks, and can be output from the clkout pin. (7) watchdog timer clock control this circuit divides the main clock oscillation frequency (f x ) by 16 to generate the clock to be supplied to the watchdog timer (f xw ). the watchdog timer is stopped when the subclock is used.
chapter 6 clock generation function user?s manual u16237ej3v0ud 143 6.3 register (1) processor clock control register (pcc) the processor clock control register (pcc) is a special regist er. data can be written to it only in combination of specific sequences (see 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. the cls bit is a read-only bit. reset sets this register to 03h. frc used not used frc 0 1 selects internal feedback resistor of subclock pcc mck mfrc cls note ck3 0 ck1 ck0 oscillation enabled oscillation stopped mck 0 1 controls main clock oscillator used not used mfrc 0 1 selects internal feedback resistor of main clock after reset: 03h r/w address: fffff828h main clock operation subclock operation cls note 0 1 status of cpu clock (f cpu ) f x f xx /2 f xx /4 f xx /8 f xt (subclock: 32.768 khz) selects clock ( f cpu ) ck1 0 0 1 1 x ck0 0 1 0 1 x ck3 0 0 0 0 1 ? even if the mck bit is set to 1 while the system is operating with the main clock as the cpu clock, the operation of the main system clock does not stop. it stops after the cpu clock has been changed to the subclock. ? when the main clock is stopped and the device is operating on the subclock, clear the mck bit to 0 and wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. <6> <7> <5> <4> <3> note the cls bit is a read-only bit. cautions 1. do not change the cpu clock (by using the ck3, ck1, and ck0 bits of the pcc register) while clkout is being output. 2. be sure to clear bit 2 to ?0?. 3. when the cpu is operating on the subclock a nd when a clock is not input to x1 or the main oscillator is stopped, do not access the registers th at cause a wait. if a wait is generated, only a reset can release the wait. remark x: don?t care
chapter 6 clock generation function user?s manual u16237ej3v0ud 144 (a) example of setting main clock operation subclock operation <1> ck3 bit 1: a bit manipulation instruction is recommended. do not change the ck1 and ck0 bits. <2> subclock operation: read the cls bit to co nfirm whether the operation has switched to the subclock. the following is the time required for switching to subclock operation after the ck3 bit is set. maximum: 1/f xt (1/subclock frequency) <3> mck bit 1: set the mck bit to 1 only when stopping the main clock. [description example] <1> _set_sub_run : st.b r0, prcmd[r0] set1 3, pcc[r0] -- ck3 bit 1 <2> _check_cls : tst1 4, pcc[r0] -- wait until the mode is changed bz _check_cls to subclock operation <3> _stop_main_clock : st.b r0, prcmd[r0] set1 6, pcc[r0] -- mck bit 1, the main clock stops
chapter 6 clock generation function user?s manual u16237ej3v0ud 145 (b) example of setting subclock operation main clock operation <1> mck bit 0: main clock oscillation starts <2> insert waits by program and wait until the oscillati on stabilization time of the main clock has elapsed. <3> ck3 bit 0: a bit manipulation instruction is recommended. do not change the ck1 and ck0 bits. <4> main clock operation: after the ck3 bit has been set, it takes the following time until the cpu starts operating on the main clock. maximum: 1/f xt (1/subclock frequency) therefore, insert one nop instruction immediately after the ck3 bit is cleared to 0 or read the cls bit to confirm that the cpu has started to operate on the main clock. [description example] <1> _start_main_osc : st.b r0, prcmd[r0] -- release protection of special register c1r1 6, pcc[r0] -- main clock oscillation starts <2> movea 0x55, r0, r11 -- wait for oscillation stabilization time _wait_ost : nop nop nop addi -1, r11, r11 mp r0, r11 bne _program_wait <3> st.b r0, prcmd[r0] c1r1 3, pcc[r0] -- ck3 0 <4> _check_cls : tst1 4, pcc[r0] -- wait until cpu starts to operate on main clock bns _check_cls
chapter 6 clock generation function user?s manual u16237ej3v0ud 146 6.4 operation 6.4.1 operation of each clock the following table shows the oper ation status of each clock. table 6-1. operation status of each clock cls bit = 0 mck bit = 0 cls bit = 1 mck bit = 0 cls bit = 1 mck bit = 1 during reset during oscillation stabilization time count halt mode idle mode software stop mode subclock mode sub-idle mode subclock mode sub-idle mode sub- software stop mode main resonator (f x ) sub-resonator (f xt ) cpu clock (f cpu ) internal system clock (f clk ) peripheral clock (f x to f x /512) wdt clock (f xw ) note rtc clock (f xt ) note the watchdog timer clock (f xw ) is operable but it stops operating in the watchdog timer if the cls bit is set to 1. remark : operable : stops 6.4.2 clock output function the clock output function allows the clkout pin to output the internal system clock (f clk ). the internal system clock (f clk ) is selected by using the pcc.ck3, pcc.ck1, and pcc.ck0 bits. the clkout pin functions alternately as the pcm1 pin and operates as a clock output pin when the pmccm register is set (see 4.3.7 port cm ). the status of the clkout pin is the same as the internal system clock in table 6-1, and can output the clock when it is (operable). when it is (stops), it outputs a low level. however, the port mode (pcm1: input mode) is selected until the clkout pin is set after reset. consequ ently, the pin goes into a high-impedance state. 6.4.3 external clock input function an external clock can be directly input to the oscillator. input the clock to the x1 pin and its inverse signal to the x2 pin. set the mfrc bit of the pcc regist er to 1 (on-chip feedback resistor not used). note, however, that oscillation stabilization time is inserted even in the external clock mode. pll register setting and operation status clock
user?s manual u16237ej3v0ud 147 chapter 7 16-bit timer/event counters 00 to 03 in the v850es/pm1, four channels of 16- bit timer/event counter 0 are provided. 7.1 functions 16-bit timer/event counter 0n has the following functions (n = 0 to 3). (1) interval timer 16-bit timer/event counter 0n generates an inte rrupt request at the preset time interval. (2) square-wave output 16-bit timer/event counter 0n can output a square wave with any selected frequency. (3) external event counter 16-bit timer/event counter 0n c an measure the number of pulses of an externally input signal. (4) one-shot pulse output (16-bit timer/event counters 00 and 01 only) 16-bit timer/event counter 0n can output a one-shot pulse whose output pulse width can be set freely. (5) ppg output 16-bit timer/event counter 0n can out put a rectangular wave whose frequency and output pulse width can be set freely. (6) pulse width measurement 16-bit timer/event counter 0n can measure the pulse width of an externally input signal.
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 148 7.2 configuration 16-bit timer/event counter 0n includes the following hardware. table 7-1. configuration of 16-bit timer/event counter 0n item configuration timer/counter 16-bit timer counter 0n 1 (tm0n) register 16-bit timer capture/ compare registers: 16-bit 2 (cr0n0, cr0n1) timer input 2 (ti0n0, ti0n1 pins) timer output 1 (to0n pin), output controller control registers note 16-bit timer mode control register 0n (tmc0n) capture/compare control register 0n (crc0n) 16-bit timer output control register 0n (toc0n) prescaler mode register 0n (prm0n) note to use the ti0n0, ti0n1, and to0n pin functions, see table 4-15 settings when port pins are used for alternate functions . the block diagram is shown below. figure 7-1. block diagram of 16-bit timer/event counter 0n inttm0n0 to0n inttm0n1 tl0n1 f xx tl0n0 2 crc0n2 crc0n1 crc0n0 tmc0n3 tmc0n2 tmc0n1 ovf0n ospt0n ospe0n toc0n4 lvs0n lvr0n toc0n1 toe0n match clear noise eliminator noise eliminator 16-bit timer capture/compare register 0n0 (cr0n0) 16-bit timer capture/compare register 0n1 (cr0n1) 16-bit timer counter 0n (tm0n) match internal bus count clock capture/compare control register 0n (crc0n) output controller selector timer output control register 0n (toc0n) noise eliminator 16-bit timer mode control register 0n (tmc0n) selector selector internal bus selector prescaler mode register 0n (prm0n) prm0n1 prm0n0 remarks 1. f xx : main clock frequency 2. n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 149 (1) 16-bit timer counter 0n (tm0n) the tm0n register is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of the count clock. tm0n (n = 0 to 3) 12 10 8 6 4 2 after reset: 0000h r address: tm00 fffff5c0h, tm01 fffff5d0h, tm02 fffff5e0h, tm03 fffff5f0h 14 0 13 11 9 7 5 3 15 1 the count value of the tm0n regi ster can be read by reading the tm0n register when the values of the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits are other than 00. th e value of the tm0n register is 0000h if it is read when the tmc0n3 and tmc0n2 bits are 00. the count value is reset to 0000h in the following cases. ? at reset signal generation ? if the tmc0n3 and tmc0n2 bits are cleared to 00 ? if the valid edge of the ti0n0 pin is input in the mode in which the clear & start occurs when inputting the valid edge to the ti0n0 pin ? if the tm0n register and the cr0n0 register match in the mode in which the clear & start occurs when the tm0n register and the cr0n0 register match ? the toc0n.ospt0n bit is set to 1 in one-shot pulse output mode (2) 16-bit timer capture/compare regi ster 0n0 (cr0n0), 16-bit timer captu re/compare register 0n1 (cr0n1) the cr0n0 and cr0n1 registers are 16-bit registers t hat are used with a capture function or comparison function selected by using the crc0n register. change of the value of the cr0n0 r egister while the timer is operat ing (tmc0n.tmc0n3 and tmc0n.tmc0n2 bits = other than 00) is prohibited. the value of the cr0n1 register can be changed during oper ation if the value has been set in a specific way. for details, see 7.5.1 rewriting cr0n1 regi ster during tm0n operation . these registers can be read or written in 16-bit units. reset sets these registers to 0000h. (a) 16-bit timer capture/comp are register 0n0 (cr0n0) cr0n0 (n = 0 to 3) 12 10 8 6 4 2 after reset: 0000h r/w address: cr000 fffff5c2h, cr010 fffff5d2h, cr020 fffff5e2h, cr030 fffff5f2h 14 0 13 11 9 7 5 3 15 1 remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 150 (i) when the cr0n0 register is used as a compare register the value set in the cr0n0 register is constantly co mpared with the tm0n register count value, and an interrupt request signal (inttm0n0) is generated if they match. the va lue is held until the cr0n0 register is rewritten. (ii) when the cr0n0 register is used as a capture register the count value of the tm0n register is captured to the cr0n0 register when a capture trigger is input. as the capture trigger, an edge of a phase reverse to that of the ti0n0 pin or the valid edge of the ti0n1 pin can be selected by using the crc0n or prm0n register. (b) 16-bit timer capture/comp are register 0n1 (cr0n1) cr0n1 (n = 0 to 3) 12108642 after reset: 0000h r/w address: cr001 fffff5c4h, cr011 fffff5d4h, cr021 fffff5e4h, cr031 fffff5f4h 14 0 13 11 9 7 5 3 15 1 (i) when using the cr0n1 register as a compare register the value set to the cr0n1 register and the count value of the tm0n re gister are always compared and when these values match, an interrupt re quest signal (inttm0n1) is generated. (ii) when using the cr0n1 regi ster as a capture register the tm0n register count value is captured to the cr0n1 register by inputting a capture trigger. the valid edge of the ti0n0 pin can be selected as t he capture trigger. the valid edge of the ti0n0 pin is set with the prm0n register. cautions 1. for the setting range when this register is used as a compare register, see 7.2 (2) (c) setting range when used as compare register. 2. if clearing of the tmc0n3 and tmc0n2 bits to 00 and input of the capture trigger conflict, then the captu red data is undefined. 3. to change the mode from the capture mode to the comparison mode, first clear the tmc0n3 and tmc0n2 bits to 00, and then change the setting. a value that has been once captured rema ins stored in the cr0n0 register unless the device is reset. if the mode has been changed to the comp arison mode, be sure to set a comparison value. 4. when the p11 and p12 pins are used as the pwm1 and pwm2 output pins, they cannot be used as timer output pins (to00, to01). 5. the ti0n0 and ti0n1 pins function altern ately as the p98/a8 to p915/a15 pins. to use the ti0n0 and ti0n1 pins, select the time r input function by using the pmc9m and pfc9m bits, before enabling the timer operat ion with the tmc0n register. if the pmc9m and pfc9m bits are manipulated after the ti mer starts operating, the edge cannot be detected correctly. remark n = 0 to 3, m = 8 to 15
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 151 (c) setting range when u sed as compare register when the cr0n0 or cr0n1 register is used as a compare register, set it as shown below. operation cr0n0 register cr0n1 register ? operation as interval timer ? operation as square-wave output ? operation as external event counter 0000h < n ffffh 0000h note m ffffh normally, this setting is not used. mask the match interrupt signal (inttm0n1). ? operation in the clear & start mode entered by ti0n0 pin valid edge input ? operation as free-running timer 0000h note n ffffh 0000h note m ffffh ? operation as ppg output m < n ffffh 0000h note m < n ? operation as one-shot pulse output 0000h note n ffffh (n m) 0000h note m ffffh (m n) note when 0000h is set, a match interrupt immediately after the timer operation does not occur and timer output is not changed, and the firs t match timing is as follows. a match in terrupt occurs at the timing when the timer counter (tm0n register) is changed from 0000h to 0001h. ? when the timer counter is cleared due to overflow ? when the timer counter is cleared due to ti0n0 pin valid edge (when clear & start mode is entered by ti0n0 pin valid edge input) ? when the timer counter is cleared due to compare ma tch (when clear & start mode is entered by match between tm0n and cr0n0 (cr0n0 = other than 0000h, cr0n1 = 0000h)) operation enabled (other than 00) tm0n register timer counter clear interrupt signal is not generated interrupt signal is generated timer operation enable bit interrupt request signal compare register set value (0000h) operation disabled (00) remarks 1. n: cr0n0 register set value m: cr0n1 register set value 2. for details of operation enable bits (tmc0n.tmc0n3, tmc0n.tmc0n2 bits), see 7.3 (1) 16-bit timer mode control register 0n (tmc0n) . 3. n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 152 table 7-2. capture operation of cr0n0 and cr0n1 registers external input signal capture operation ti0n0 pin input ti0n1 pin input set values of es0n1 and es0n0 position of edge to be captured set values of es0n1 and es0n0 position of edge to be captured 01: rising 01: rising 00: falling 00: falling crc0n1 bit = 1 ti0n0 pin input (reverse phase) 11: both edges (cannot be captured) crc0n1 bit = 0 ti0n1 pin input 11: both edges capture operation of cr0n0 register interrupt signal inttm0n0 signal is not generated even if value is captured. interrupt signal inttm0n0 signal is generated each time value is captured. set values of es1n1 and es1n0 position of edge to be captured 01: rising 00: falling ti0n0 pin input note 11: both edges capture operation of cr0n1 register interrupt signal inttm0n1 signal is generated each time value is captured. note the capture operation of the cr0n1 register is not affected by the setting of the crc0n1 bit. caution to capture the count value of the tm0n regi ster to the cr0n0 regist er by using the phase reverse to that input to the ti 0n0 pin, the interrupt request si gnal (inttm0n0) is not generated after the value has been captured . if the valid edge is detect ed on the ti0n1 pin during this operation, the capture operation is not performe d but the inttm0n0 signal is generated as an external interrupt signal. to not use the external interrupt, mask the inttm0n0 signal. remarks 1. crc0n1: see 7.3 (2) capture/compare control register 0n (crc0n) . es1n1, es1n0, es0n1, es0n0: see 7.3 (4) prescaler mode register 0n (prm0n) . 2. n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 153 7.3 registers registers used to control 16-bit time r/event counter 0n are shown below. ? 16-bit timer mode control register 0n (tmc0n) ? capture/compare contro l register 0n (crc0n) ? 16-bit timer output control register 0n (toc0n) ? prescaler mode register 0n (prm0n) remark to use the ti0n0, ti0n1, and to0n pin functions, see table 4-15 settings when port pins are used for alternate functions . (1) 16-bit timer mode cont rol register 0n (tmc0n) tmc0n is an 8-bit register that sets the 16-bit timer/ event counter 0n operation mode, the tm0n register clear mode, and output timing, and detects an overflow. rewriting tmc0n is prohibited during operation (w hen the tmc0n2 and tmc0n3 bits = other than 00). however, it can be changed when the tmc0n2 and tmc0 n3 bits are cleared to 00 (stopping operation) and when the ovf0n bit is cleared to 0. this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. cautions 1. 16-bit timer/event c ounter 0n starts operation at the mo ment tmc0n2 and tmc0n3 are set to values other than 00 (operation stop mode), respectively. set tmc0n2 and tmc0n3 to 00 to stop the operation. 2. when the main clock is stopped and the cpu is operating on the subclock, do not access the tmc0n register using an access method that causes a wait. for details, see 3.4.8 (2). 3. be sure to clear bits 7 to 4 to ?0?. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 154 after reset: 00h r/w address: tmc00 fffff5c6h, tmc01 fffff5d6h, tmc02 fffff5e6h, tmc03 fffff5f6h 7 6 5 4 3 2 1 <0> tmc0n 0 0 0 0 tmc0n3 tmc0n2 tmc0n1 ovf0n (n = 0 to 3) tmc0n3 tmc0n2 enable operation of 16-bit timer/event counter 0n 0 0 disables tm0n operation. stops suppl ying operating clock. clears 16-bit counter (tm0n). 0 1 free-running timer mode 1 0 clear & start mode entered by ti0n0 pin valid edge input note 1 1 clear & start mode entered upon a match between tm0n and cr0n0 tmc0n1 e nable operation of 16-bit timer/event counter 0n 0 ? match between tm0n and cr0n0 or match between tm0n and cr0n1 1 ? match between tm0n and cr0n0 or match between tm0n and cr0n1 ? trigger input of ti0n0 pin valid edge ovf0n tm0n register overflow flag clear (0) clears ovf0n to 0 or tmc0n.tmc0n3 and tmc0n.tmc0n2 = 00 set (1) overflow occurs. ovf0n is set to 1 when the value of tm0n changes from ffffh to 0000h in all the operation modes (free-running timer mode, clear & start mode entered by ti0n0 pin valid edge input, and clear & start mode entered upon a match between tm0n and cr0n0). it can also be set to 1 by writing 1 to the ovf0n bit. note the ti0n0 pin valid edge is set by the prm0n register.
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 155 (2) capture/compare control register 0n (crc0n) the crc0n register is the register that controls the operation of the cr0n0 and cr0n1 registers. changing the value of the crc0n register is prohi bited during operation (when the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits = other than 00). this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. after reset: 00h r/w address: crc00 fffff5c8h, crc01 fffff5d8h, crc02 fffff5e8h, crc03 fffff5f8h 7 6 5 4 3 2 1 0 crc0n 0 0 0 0 0 crc0n2 crc0n1 crc0n0 (n = 0 to 3) crc0n2 cr0n1 register operating mode selection 0 operates as compare register 1 operates as capture register crc0n1 cr0n0 register capt ure trigger selection 0 captures on valid edge of ti0n1 pin 1 captures on valid edge of ti0n0 pin by reverse phase note the valid edge of the ti0n1 and ti0n0 pin is set by the prm0n register. if prm0n.es0n1 and prm0n.es0n0 are set to 11 (both edges) when crc0n1 is 1, the valid edge of the ti0n0 pin cannot be detected. crc0n0 cr0n0 register operating mode selection 0 operates as compare register 1 operates as capture register if tmc0n3 and tmc0n2 are set to 11 (clear & start mode entered upon a match between tm0n and cr0n0), be sure to clear the crc0n0 bit to 0. note when the valid edge is detected from the ti0n1 pin, the capture oper ation is not performed but the inttm0n0 signal is generated as an external interrupt signal. caution to ensure that the capture operation is pe rformed properly, the cap ture trigger requires a pulse two cycles longer than the count clock selected by the prm0n register.
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 156 (3) 16-bit timer output control register 0n (toc0n) the toc0n register is an 8-bit register that controls the to0n pin output. the toc0n register can be rewritt en while only the ospt0n bit is operating (when the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits = other than 00). rewriting t he other bits is prohibited during operation. however, toc0n4 can be rewritten during timer operat ion as a means to rewrite the cr0n1 register (see 7.5.1 rewriting cr0n1 register during tm0n operation ). this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. caution be sure to set the toc0n regi ster using the following procedure. <1> set the toc0n4 and toc0n1 bits to 1. <2> set only the toe0n bit to 1. <3> set either the lvs0n bit or lvr0n bit to 1. (1/2) after reset: 00h r/w address: toc00 fffff5c9h, toc01 fffff5d9h, toc02 fffff5e9h, toc03 fffff5f9h 7 <6> <5> 4 <3> <2> 1 <0> toc0n 0 ospt0n ospe0n toc0n4 lvs0n lvr0n toc0n1 toe0n (n = 0 to 3) ospt0n one-shot pulse out put trigger via software 0 ? 1 one-shot pulse output the value of this bit is always ?0? when it is read. if it is set to 1, tm0n is cleared and started. ospe0n one-shot pulse output operation control 0 successive pulse output 1 one-shot pulse output one-shot pulse output operates correctly in the fr ee-running timer mode or clear & start mode entered by ti0n0 pin valid edge input. the one-shot pulse cannot be output in the clear & start mode entered upon a match between the tm0n and cr0n0 registers. toc0n4 to0n pin output control on match between cr0n1 and tm0n registers 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm0n1) is generated even when the toc0n4 bit = 0.
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 157 (2/2) lvs0n lvr0n setting of to0n pin output status 0 0 no change 0 1 initial value of to0n pin output is low level (to0n pin output is cleared to 0). 1 0 initial value of to0n pin output is high level (to0n pin output is set to 1). 1 1 setting prohibited ? the lvs0n and lvr0n bits can be used to set the initial value of the output level of the to0n pin. if the initial value does not have to be set, leave the lvs0n and lvr0n bits as 00. ? be sure to set the lvs0n and lvr0n bits when toe0n = 1. the lvs0n, lvr0n, and toe0n bits being simultaneously set to 1 is prohibited. ? the lvs0n and lvr0n bits are trigger bits. by sett ing these bits to 1, the initial value of the output level of the to0n pin can be set. even if these bits are cleared to 0, output of the to0n pin is not affected. ? the values of the lvs0n and lvr0n bits are always 0 when they are read. ? for how to set the lvs0n and lvr0n bits, see 7.5.2 setting lvs0n and lvr0n bits . toc0n1 to0n pin output control on match between cr0n0 and tm0n registers 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm0n0) is generated even when the toc0n1 bit = 0. toe0n to0n pin output control 0 disables output (to0n pin output fixed to low level) 1 enables output
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 158 (4) prescaler mode register 0n (prm0n) the prm0n register is the register that sets the tm 0n register count clock and ti0n0 and ti0n1 pin input valid edges. rewriting the prm0n register is prohibited durin g operation (when the tmc 0n.tmc0n3 and tmc0n.tmc0n2 bits = other than 00). this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. cautions 1. do not apply the following setting when setting the prm0n1 and pr m0n0 bits to 11 (to specify the valid edge of th e ti0n0 pin as a count clock). ? clear & start mode entered by the ti0n0 pin valid edge ? setting the ti0n0 pin as a capture trigger 2. if the operation of 16-bit ti mer/event counter 0n is enabled when the ti0n0 or ti0n1 pin is at high level and when the valid edge of the ti0n0 or ti0n1 pin is specified to be the rising edge or both edges, the high level of th e ti0n0 or ti0n1 pin is detected as a rising edge. note this when the ti0n0 or ti0n1 pin is pulled up. however, the rising edge is not detected when the timer oper ation has been once stopped a nd is then enabled again. 3. when the p11 and p12 pins are used as the pwm1 and pwm2 output pins, they cannot be used as timer output pins (to00, to01). (n = 0 to 3) es1n1 es1n0 ti0n1 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es0n1 es0n0 ti0n0 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges remark for settings of the prm0n1 and prm0n0 bits, see (a) and (b) on the next page. after reset: 00h r/w address: prm00 fffff5c7h, prm01 fffff5d7h, prm02 fffff5e7h, prm03 fffff5f7h 7 6 5 4 3 2 1 0 prm0n es1n1 es1n0 es0n1 es0n0 0 0 prm0n1 prm0n0
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 159 (a) count clock for 16-bit timer/event counters 00 and 01 selection of count clock prm0n1 bit prm0n0 bit count clock f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 0 0 f xx /4 200 ns 250 ns 400 ns 0 1 f xx /16 800 ns 1.0 s 1.6 s 1 0 f xx /32 1.6 s 2.0 s 3.2 s 1 1 valid edge of ti0n0 note ? ? ? note the external clock requires a pulse longer than two cycles of the internal clock (f xx ). remark n = 0, 1 (b) count clock for 16-bit timer/event counters 02 and 03 selection of count clock prm0n1 bit prm0n0 bit count clock f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 0 0 f xx /4 200 ns 250 ns 400 ns 0 1 f xx /2 10 51.2 s 64 s 102.4 s 1 0 f xx /2 11 102.4 s 128 s 204.8 s 1 1 valid edge of ti0n0 note ? ? ? note the external clock requires a pulse longer than two cycles of the internal clock (f xx ). remark n = 0, 1
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 160 7.4 operation 7.4.1 interval timer operation if the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits are set to 11 (clear & start mode entered upon a match between the tm0n register and the cr0n0 register), the count operation is started in synchronization with the count clock. when the value of the tm0n register late r matches the value of the cr0n0 regist er, the tm0n register is cleared to 0000h and a match interrupt signal (inttm0n0) is generat ed. this inttm0n0 signal enables the tm0n register to operate as an interval timer. remarks 1. for the alternate-function pin settings, see table 4-15 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 interrupt, see chapter 16 interrupt/exception processing function . figure 7-2. block diagram of interval timer operation 16-bit counter (tm0n) cr0n0 register operable bits tmc0n3, tmc0n2 count clock clear match signal inttm0n0 signal remark n = 0 to 3 figure 7-3. basic timing exampl e of interval timer operation tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr0n0) compare match interrupt (inttm0n0) n 11 00 n n n n interval (n + 1) interval (n + 1) interval (n + 1) interval (n + 1) remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 161 figure 7-4. example of register se ttings for interval timer operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 ovf0n clears and starts on match between tm0n and cr0n0. (b) capture/compare contro l register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr0n0 used as compare register (c) 16-bit timer output control register 0n (toc0n) 00000 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 000 (d) prescaler mode register 0n (prm0n) 00000 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock. 0 0/1 0/1 (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) if m is set to the cr0n0 register, the interval time is as follows. (m + 1) count clock cycle clearing the cr0n0 register to 0000h is prohibited. (g) 16-bit capture/compare register 0n1 (cr0n1) usually, the cr0n1 register is not used for the inte rval timer function. however, a compare match interrupt (inttm0n1) is generated when the set value of the cr0n1 register ma tches the value of the tm0n register. therefore, mask the interrupt request by using the interrupt mask flag (tmmk0n1). remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 162 figure 7-5. example of software pr ocessing for interval timer function tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr0n0) compare match interrupt (inttm0n0) n 11 00 00 n n n <1> <2> tmc0n3, tmc0n2 bits = 11 tmc0n3, tmc0n2 bits = 00 register initial setting prm0n register, crc0n register, cr0n0 register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. start stop <1> count operation start flow <2> count operation stop flow remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 163 7.4.2 square wave output operation when 16-bit timer/event counter 0n operates as an interval timer (see 7.4.1 ), a square wave can be output from the to0n pin by setting the toc0n register to 03h. when the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits are set to 11 (count clear & start mode entered upon a match between the tm0n register and the cr0n0 register), the c ounting operation is started in synchronization with the count clock. when the value of the tm0n register late r matches the value of the cr0n0 regist er, the tm0n register is cleared to 0000h, an interrupt signal (inttm0n0) is generated, and output of the to0n pin is invert ed. this to0n pin output that is inverted at fixed interval s enables to0n to output a square wave. remarks 1. for the alternate-function pin settings, see table 4-15 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 interrupt, see chapter 16 interrupt/exception processing function . figure 7-6. block diagram of square wave output operation 16-bit counter (tm0n) cr0n0 register operable bits tmc0n3, tmc0n2 count clock clear match signal inttm0n0 signal output controller to0n pin remark n = 0 to 3 figure 7-7. basic timing example of square wave output operation tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr0n0) to0n pin output compare match interrupt (inttm0n0) n 11 00 n n n n interval (n + 1) interval (n + 1) interval (n + 1) interval (n + 1) remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 164 figure 7-8. example of register setti ngs for square wave output operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 ovf0n clears and starts on match between tm0n and cr0n0. (b) capture/compare contro l register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr0n0 used as compare register (c) 16-bit timer output control register 0n (toc0n) 00000 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n pin output. inverts to0n pin output on match between tm0n and cr0n0. specifies the initial value of to0n output f/f. 011 (d) prescaler mode register 0n (prm0n) 00000 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock. 0 0/1 0/1 (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) if m is set to the cr0n0 register, the square wave frequency is as follows. 1 / [2 (m + 1) count clock cycle] clearing the cr0n0 register to 0000h is prohibited. (g) 16-bit capture/compare register 0n1 (cr0n1) usually, the cr0n1 register is not used for the s quare wave output function. however, a compare match interrupt (inttm0n1) is generated when the se t value of the cr0n1 register matches the value of the tm0n register. therefore, mask the interrupt request by using the interrupt mask flag (tmmk0n1). remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 165 figure 7-9. example of software proc essing for square wave output function tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr0n0) to0n pin output compare match interrupt (inttm0n0) to0n output control bit (toc0n1, toe0n) n 11 00 00 n n n <1> <2> tmc0n3, tmc0n2 bits = 11 tmc0n3, tmc0n2 bits = 00 register initial setting prm0n register, crc0n register, toc0n register note , cr0n0 register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 11. starts count operation. the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. start stop <1> count operation start flow <2> count operation stop flow note care must be exercised when setting the toc0n register. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 166 7.4.3 external event counter operation when the prm0n.prm0n1 and prm0n.prm0n0 bits are set to 11 (for counting up with the valid edge of the ti0n0 pin) and the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits are se t to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matc hing between the tm0n register and the cr0n0 register (inttm0n0) is generated. to input the external event, the ti0n0 pin is used. th erefore, the timer/event co unter cannot be used as an external event counter in the clear & start mode entered by the ti0n0 pin va lid edge input (when the tmc0n3 and tmc0n2 bits = 10). the inttm0n0 signal is generated with the following timing. ? valid edge of external event input (set value of the cr0n0 register + 1) however, the first match interrupt immediately after the timer/event counter has start ed operating is generated with the following timing. ? valid edge of external event input (set value of the cr0n0 register + 2) to detect the valid edge, the signal input to the ti0n0 pin is sampled during the clock cycle of f xx . the valid edge is not detected until it is detected two times in a row. t herefore, a noise with a short pul se width can be eliminated. remarks 1. for the alternate-function pin (ti0n0) settings, see table 4-15 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 interrupt, see chapter 16 interrupt/exception processing function . figure 7-10. block diagram of ex ternal event counter operation 16-bit counter (tm0n) cr0n0 register operable bits tmc0n3, tmc0n2 clear match signal inttm0n0 signal f xx edge detection ti0n0 pin output controller to0n pin remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 167 figure 7-11. example of register setti ngs in external event counter mode (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 ovf0n clears and starts on match between tm0n and cr0n0. (b) capture/compare contro l register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr0n0 used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 0 0 0/1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 0: disables to0n output. 1: enables to0n output. 00: does not invert to0n output on match between tm0n and cr0n0/cr0n1. 01: inverts to0n output on match between tm0n and cr0n0. 10: inverts to0n output on match between tm0n and cr0n1. 11: inverts to0n output on match between tm0n and cr0n0/cr0n1. specifies initial value of to0n output f/f. 0/1 0/1 0/1 (d) prescaler mode register 0n (prm0n) 0 0 0/1 0/1 0 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock (specifies valid edge of ti0n0). 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 011 (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) if m is set to the cr0n0 register, the interrupt si gnal (inttm0n0) is generated when the number of external events reaches (m + 1). clearing the cr0n0 register to 0000h is prohibited. (g) 16-bit capture/compare register 0n1 (cr0n1) when this register?s value matches the count value of the tm0n register, an interrupt signal (inttm0n1) is generated. the count value of the tm0n register is not cleared. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 168 figure 7-12. example of software proce ssing in external event counter mode compare register (cr0n0) operable bits (tmc0n3, tmc0n2) 0000h tm0n register to0n pin output compare match interrupt (inttm0n0) to0n output control bit (toc0n4, toc0n1, toe0n) tmc0n3, tmc0n2 bits = 11 tmc0n3, tmc0n2 bits = 00 register initial setting prm0n register, crc0n register, toc0n register note , cr0n0 register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 11. starts count operation. the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. start stop <1> count operation start flow <2> count operation stop flow 11 00 n n n n 00 <1> <2> note care must be exercised when setting the toc0n register. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 169 7.4.4 operation in clear & start mode entered by ti0n0 pin valid edge input when the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits are set to 10 (clear & start mode entered by the ti0n0 pin valid edge input) and the count clock (set by the prm0n regi ster) is supplied to the timer/event counter, the tm0n register starts counting up. when the valid edge of the ti0n0 pin is detected during the counting operation, the tm0n register is cleared to 0000h and starts counting up again. if the valid edge of the ti0n0 pin is not detected, the tm0n register overflows and continues counting. the valid edge of the ti0n0 pin is a cause to clear th e tm0n register. starting the counter is not controlled immediately after the st art of the operation. the cr0n0 and cr0n1 registers are used as compare registers and capture registers. (a) when the cr0n0 and cr0n1 regist ers are used as compare registers signals inttm0n0 and inttm0n1 are generated when the value of the tm0n register matches the value of the cr0n0 and cr0n1 registers. (b) when the cr0n0 and cr0n1 regist ers are used as capture registers the count value of the tm0n register is captured to the cr0n0 regist er and the inttm0n0 signal is generated when the valid edge is input to the ti0n1 pin (or when the phase reverse to that of the valid edge is input to the ti0n0 pin). when the valid edge is input to the ti 0n0 pin, the count value of the tm0n register is captured to the cr0n1 register and the inttm0n1 signal is generated. as soon as the count value has been captured, the counter is cleared to 0000h. caution do not set the count clock as the va lid edge of the ti0n0 pin (rpm0n.prm0n1 and rpm0n.prm0n0 bits = 11). when the prm0n1 a nd prm0n0 bits = 11, the tm0n register is cleared. remarks 1. for the alternate-function pin (ti0n0) settings, see table 4-15 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 interrupt, see chapter 16 interrupt/exc eption processing function .
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 170 (1) operation in clear & start mode en tered by ti0n0 pin valid edge input (cr0n0 register: compare register , cr0n1 register: compare register) figure 7-13. block diagram of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: compare register , cr0n1 register: compare register) 16-bit counter (tm0n) clear output controller edge detection compare register (cr0n1) match signal to0n pin match signal interrupt signal (inttm0n0) interrupt signal (inttm0n1) ti0n0 pin compare register (cr0n0) operable bits tmc0n3, tmc0n2 count clock remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 171 figure 7-14. timing example of clear & star t mode entered by ti0n0 pin valid edge input (cr0n0 register: compare register , cr0n1 register: compare register) (a) toc0n = 13h, prm0n = 10h, crc0n = 00h, tmc0n = 08h tm0n register 0000h operable bits (tmc0n3, tmc0n2) count clear input (ti0n0 pin input) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) to0 n pin output m 10 m nn nn mmm 00 n (b) toc0n = 13h, prm0n = 10h, crc0n = 00h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) count clear input (ti0n0 pin input) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) to0n pin output m 10 m nn nn mmm 00 n (a) and (b) differ as follows depending on the setting of the tmc0n register (tmc0n1 bit). (a) the output level of the to0n pi n is inverted when the tm0n register matches a compare register. (b) the output level of the to0n pin is inverted w hen the tm0n register matches a compare register or when the valid edge of the ti0n0 pin is detected. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 172 (2) operation in clear & start mode en tered by ti0n0 pin valid edge input (cr0n0 register: compare register , cr0n1 register: capture register) figure 7-15. block diagram of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: compare register, cr0n1 register: capture register) 16-bit counter (tm0n) clear output controller edge detector capture register (cr0n1) capture signal to0n pin match signal interrupt signal (inttm0n0) interrupt signal (inttm0n1) ti0n0 pin compare register (cr0n0) operable bits tmc0n3, tmc0n2 count clock remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 173 figure 7-16. timing example of clear & star t mode entered by ti0n0 pin valid edge input (cr0n0 register: compare register, cr0n1 register: capture register) (1/2) (a) toc0n = 13h, prm0n = 10h, crc0n = 04h, tmc0n = 08h, cr0n0 = 0000h tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0 pin input) compare register (cr0n0) compare match interrupt (inttm0n0) capture register (cr0n1) capture interrupt (inttm0n1) to0n pin output 0000h 10 q p n m s 00 0000h m n s p q this is an application example where the output level of t he to0n pin is inverted when the count value has been captured & cleared. the count value is captured to the cr0n1 register an d the tm0n register is cleared (to 0000h) when the valid edge of the ti0n0 pin is det ected. when the count va lue of the tm0n register is 0000h, a compare match interrupt signal (inttm0n0) is generated, and t he output level of the to0n pin is inverted. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 174 figure 7-16. timing example of clear & star t mode entered by ti0n0 pin valid edge input (cr0n0 register: compare register, cr0n1 register: capture register) (2/2) (b) toc0n = 13h, prm0n = 10h, crc0n = 04h, tmc0n = 0ah, cr0n0 = 0003h tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0 pin input) compare register (cr0n0) compare match interrupt (inttm0n0) capture register (cr0n1) capture interrupt (inttm0n1) to0n pin output 0003h 0003h 10 q p n m s 00 0000h m 4444 ns pq this is an application exampl e where the width set to the cr0n0 register (4 clocks in this example) is to be output from the to0n pin when the count value has been captured & cleared. the count value is captured to the cr0n1 register, a capture interrupt signal (inttm0n1) is generated, the tm0n register is cleared (to 0000h), and the output level of the to0n pin is inverted when the valid edge of the ti0n0 pin is detected. when the count value of the tm 0n register is 0003h (four clocks have been counted), a compare match interrupt signal (inttm0n0) is generat ed and the output level of the to0n pin is inverted. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 175 (3) operation in clear & start mode en tered by ti0n0 pin valid edge input (cr0n0 register: capture register , cr0n1 register: compare register) figure 7-17. block diagram of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: capture register , cr0n1 register: compare register) 16-bit counter (tm0n) clear output controller edge detection capture register (cr0n0) capture signal to0n pin match signal interrupt signal (inttm0n1) interrupt signal (inttm0n0) ti0n0 pin compare register (cr0n1) operable bits tmc0n3, tmc0n2 count clock remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 176 figure 7-18. timing example of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: capture register, cr0n1 register: compare register) (1/2) (a) toc0n = 13h, prm0n = 10h, crc0n = 03h, tmc0n = 08h, cr0n1 = 0000h 10 p n m s 00 l 0000h 0000h mns p tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0 pin input) capture register (cr0n0) capture interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) to0n pin output this is an application example where the output level of the to0n pin is to be inverted when the count value has been captured & cleared. the tm0n register is cleared at the rising edge detecti on of the ti0n0 pin and it is captured to the cr0n0 register at the falling edge detection of the ti0n0 pin. when the crc0n.crc0n1 bit is set to 1, the count value of the tm0n register is captured to cr0n0 in the phase reverse to that of the signal input to the ti0n0 pi n, but the capture interrupt signal (inttm0n0) is not generated. however, the inttm0n0 signal is generated when the valid edge of the ti0n1 pin is detected. mask the inttm0n0 signal when it is not used. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 177 figure 7-18. timing example of clear & star t mode entered by ti0n0 pin valid edge input (cr0n0 register: capture register, cr0n1 register: compare register) (2/2) (b) toc0n = 13h, prm0n = 10h, crc0n = 03h, tmc0n = 0ah, cr0n1 = 0003h tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0 pin input) capture register (cr0n0) capture interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) to0n pin output 0003h 0003h 10 p n m s 00 4444 l 0000h m n s p this is an application exampl e where the width set to the cr0n1 register (4 clocks in this example) is to be output from the to0n pin when the count value has been captured & cleared. the tm0n register is cleared (to 0000h) at the rising edge detection of the ti 0n0 pin and captured to the cr0n0 register at the falling edge detec tion of the ti0n0 pin. the output level of the to0n pin is inverted when the tm0n register is cleared (to 0000h) because the rising edge of the ti0n0 pin has been detected or when the value of the tm0n register matches that of a compare register (cr0n1). when the crc0n.crc0n1 bit is 1, the count value of the tm0n register is captured to the cr0n0 register in the phase reverse to that of the input signal of the ti0n0 pin, but the captur e interrupt signal (inttm0n0) is not generated. however, the inttm0n0 inte rrupt is generated when the valid edg e of the ti0n1 pin is detected. mask the inttm0n0 signal when it is not used. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 178 (4) operation in clear & start mode en tered by ti0n0 pin valid edge input (cr0n0 register: capture register , cr0n1 register: capture register) figure 7-19. block diagram of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: capture register , cr0n1 register: capture register) 16-bit counter (tm0n) clear output controller capture register (cr0n0) capture signal capture signal to0n pin interrupt signal (inttm0n1) interrupt signal (inttm0n0) capture register (cr0n1) operable bits tmc0n3, tmc0n2 count clock edge detection ti0n0 pin edge detection ti0n1 pin selector remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 179 figure 7-20. timing example of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: capture register, cr0n1 register: capture register) (1/3) (a) toc0n = 13h, prm0n = 30h, crc0n = 05h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0 pin input) capture register (cr0n0) capture interrupt (inttm0n0) capture register (cr0n1) capture interrupt (inttm0n1) to0n pin output 10 r s t o l m n p q 00 l 0000h 0000h lm nopqrst this is an application example where t he count value is captured to the cr0n1 register, the tm0n register is cleared, and the to0n pin output is inverted when the rising or falling edge of t he ti0n0 pin is detected. when the edge of the ti0n1 pin is det ected, an interrupt signal (inttm 0n0) is generated. mask the inttm0n0 signal when it is not used. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 180 figure 7-20. timing example of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: capture register, cr0n1 register: capture register) (2/3) (b) toc0n = 13h, prm0n = c0h, crc0n = 05h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n1 pin input) capture register (cr0n0) capture interrupt (inttm0n0) capture & count clear input (ti0n0) capture register (cr0n1) capture interrupt (inttm0n1) to0n pin output 10 r s t o l m n p q 00 ffffh l l l 0000h 0000h lmn o pq r s t this is a timing example where an edge is not input to the ti0n0 pin, in an application where the count value is captured to the cr0n0 register when the rising or falling edge of the ti0n1 pin is detected. because the to0n0 pin does not detect any edges, the to0n pin output is not inverted and remains low level. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 181 figure 7-20. timing example of clear & start mode entered by ti0n0 pin valid edge input (cr0n0 register: capture register, cr0n1 register: capture register) (3/3) (c) toc0n = 13h, prm0n = 00h, crc0n = 07h, tmc0n = 0ah tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0 pin input) capture register (cr0n0) capture register (cr0n1) capture interrupt (inttm0n1) to0n pin output capture input (ti0n1) capture interrupt (inttm0n0) 0000h 10 p o m q r t s w n l 00 l l ln r pt 0000h moq sw this is an application example where the pulse width of the signal input to the ti0n0 pin is measured. by setting the crc0n register, the count value can be captured to the cr0n0 register in the phase reverse to the falling edge of the ti0n0 pin (i.e., rising edge) and to the cr0n1 register at the falling edge of the ti0n0 pin. the high- and low-level widths of the input pulse can be calculated by the following expressions. ? high-level width = [cr0n1 register value] ? [cr0n0 register value] [count clock cycle] ? low-level width = [cr0n0 register value] [count clock cycle] if the reverse phase of the ti0n0 pin is selected as a trigger to capture the count value to the cr0n0 register, the inttm0n0 signal is not generated. read the values of the cr0n0 and cr0n1 registers to measure the pulse width immediately after the inttm0n1 signal is generated. however, if the valid edge specified by the prm0n.es1 n1 and prm0n.es1n0 bits is input to the ti0n1 pin, the count value is not captured but the inttm0n0 signal is generated. to measure the pulse width of the ti0n0 pin, mask the inttm0n0 signal when it is not used. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 182 figure 7-21. example of register settings in clear & st art mode entered by ti0n0 pin valid edge input (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 0000100/10 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts at valid edge input of ti0n0 pin. 0: inverts to0n output on match between cr0n0 and cr0n1. 1: inverts to0n output on match between cr0n0 and cr0n1 and valid edge of ti0n0 pin. (b) capture/compare contro l register 0n (crc0n) 000000/10/10/1 crc0n2 crc0n1 crc0n0 0: cr0n0 used as compare register 1: cr0n0 used as capture register 0: cr0n1 used as compare register 1: cr0n1 used as capture register 0: ti0n1 pin is used as capture trigger of cr0n0. 1: reverse phase of ti0n0 pin is used as capture trigger of cr0n0. (c) 16-bit timer output control register 0n (toc0n) 0 0 0 0/1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 0: disables to0n output 1: enables to0n output 00: does not invert to0n output on match between tm0n and cr0n0/cr0n1. 01: inverts to0n output on match between tm0n and cr0n0. 10: inverts to0n output on match between tm0n and cr0n1. 11: inverts to0n output on match between tm0n and cr0n0/cr0n1. specifies initial value of to0n output f/f 0/1 0/1 0/1 remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 183 figure 7-21. example of register settings in clear & st art mode entered by ti0n0 pin valid edge input (2/2) (d) prescaler mode register 0n (prm0n) 0/1 0/1 0/1 0/1 0 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 count clock selection (setting ti0n0 valid edge is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting prohibited when crc0n1 = 1) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) when this register is used as a compare register and when its value matches the count value of the tm0n register, an interrupt signal (inttm0n0) is generat ed. the count value of t he tm0n register is not cleared. to use this register as a capture register, select ei ther the ti0n0 or ti0n1 pin i nput as a capture trigger. when the valid edge of the capture trig ger is detected, the count value of the tm0n register is stored in the cr0n0 register. (g) 16-bit capture/compare register 0n1 (cr0n1) when this register is used as a compare register and when its value matches the count value of the tm0n register, an interrupt signal (inttm0n1) is generat ed. the count value of t he tm0n register is not cleared. when this register is used as a capture register, t he ti0n0 pin input is used as a capture trigger. when the valid edge of the capture trigger is detected, the count value of the tm0n register is stored in the cr0n1 register. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 184 figure 7-22. example of software processing in clear & start mode entered by ti 0n0 pin valid edge input tm0n register 0000h operable bits (tmc0n3, tmc0n2) count clear input (ti0n0 pin input) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) to0n pin output m 10 m n n n n mmm 00 <1> <2> <2> <2> <3> <2> 00 n tmc0n3, tmc0n2 bits = 10 edge input to ti0n0 pin register initial setting prm0n register, crc0n register, toc0 n register note , cr0n0, cr0n1 registers, tmc0n.tmc0n1 bit, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 10. starts count operation when the valid edge is input to the ti0n0 pin, the value of the tm0n register is cleared. start <1> count operation start flow <2> tm0n register clear & start flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <3> count operation stop flow note care must be exercised when setting the toc0n register. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 185 7.4.5 free-running timer operation when the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits are set to 01 (free-running timer mode), 16-bit timer/event counter 0n continues counting up in synchronization with t he count clock. when it has counted up to ffffh, the overflow flag (tmc0n.ovf0n bit) is set to 1 at the nex t clock, and the tm0n register is cleared (to 0000h) and continues counting. clear the ovf0n bit to 0 by executing the clr instruction via software. the following three types of free-runn ing timer operations are available. ? both the cr0n0 and cr0n1 register s are used as compare registers. ? either the cr0n0 register or cr0n1 register is used as a compare register and the other is used as a capture register. ? both the cr0n0 and cr0n1 register s are used as capture registers. remarks 1. for the alternate-function pin (to0n) settings, see table 4-15 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 and inttm0n1 interrupts, see chapter 16 interrupt/exception processing function . (1) free-running timer mode operation (cr0n0 register: compare register , cr0n1 register: compare register) figure 7-23. block diagram of free-running timer mode (cr0n0 register: compare register, cr0n1 register: compare register) 16-bit counter (tm0n) output controller compare register (cr0n1) match signal to0n pin match signal interrupt signal (inttm0n0) interrupt signal (inttm0n1) compare register (cr0n0) operable bits tmc0n3, tmc0n2 count clock remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 186 figure 7-24. timing example of free-running timer mode (cr0n0 register: compare register, cr0n1 register: compare register) ? toc0n = 13h, prm0n = 00h, crc0n = 00h, tmc0n = 04h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) to0n pin output overflow flag (ovf0n) 01 m n m n m n m n 00 00 n 0 write clear 0 write clear 0 write clear 0 write clear m this is an application example where two compare registers are used in the free-running timer mode. the output level of the to0n pin is reversed each time the count value of the tm0n register matches the set values of the cr0n0 and cr0n1 registers. when the coun t value matches the register value, the inttm0n0 or inttm0n1 signal is generated. remark n = 0 to 3 (2) free-running timer mode operation (cr0n0 register: compare register , cr0n1 register: capture register) figure 7-25. block diagram of free-running timer mode (cr0n0 register: compare register, cr0n1 register: capture register) 16-bit counter (tm0n) edge detection capture register (cr0n1) capture signal match signal interrupt signal (inttm0n0) interrupt signal (inttm0n1) ti0n0 pin compare register (cr0n0) operable bits tmc0n3, tmc0n2 count clock remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 187 figure 7-26. timing example of free-running timer mode (cr0n0 register: compare register, cr0n1 register: capture register) ? toc0n = 13h, prm0n = 10h, crc0n = 04h, tmc0n = 04h 01 m n s p q 00 0000h 0000h mn s p q ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n0) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) capture interrupt (inttm0n1) to0n pin output overflow flag (ovf0n) 0 write clear 0 write clear 0 write clear 0 write clear this is an application example where a compare register a nd a capture register are used at the same time in the free-running timer mode. in this example, the inttm0n0 signal is generated and th e output level of the to0n pin is reversed each time the count value of the tm0n register matches the set value of the cr0n0 register (compare register). in addition, the inttm0n1 signal is generated and the count va lue of the tm0n register is captured to the cr0n1 register each time the valid ed ge of the ti0n0 pin is detected. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 188 (3) free-running timer mode operation (cr0n0 register: capture register , cr0n1 register: capture register) figure 7-27. block diagram of free-running timer mode (cr0n0 register: capture register, cr0n1 register: capture register) 16-bit counter (tm0n) capture register (cr0n0) capture signal capture signal interrupt signal (inttm0n1) interrupt signal (inttm0n0) capture register (cr0n1) operable bits tmc0n3, tmc0n2 count clock edge detection ti0n0 pin edge detection ti0n1 pin selector remarks 1. if both the cr0n0 and cr0n1 registers are used as capture registers in the free-running timer mode, the output level of t he to0n pin is not inverted. however, it can be inverted each time the valid edge of the ti0n0 pin is detected if the tmc0n.tmc0n1 bit is set to 1. 2. n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 189 figure 7-28. timing example of free-running timer mode (cr0n0 register: capture register, cr0 n1 register: capture register) (1/2) (a) toc0n = 13h, prm0n = 50h, crc0n = 05h, tmc0n = 04h 01 m a b c de n s p q 00 0000h abc d e 0000h mn s p q ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n0) capture register (cr0n1) capture interrupt (inttm0n1) capture trigger input (ti0n1) capture register (cr0n0) capture interrupt (inttm0n0) overflow flag (ovf0n) 0 write clear 0 write clear 0 write clear 0 write clear this is an application example where the count values that have been captured at the valid edges of separate capture trigger signals are stor ed in separate capture registers in the free-running timer mode. the count value is captured to the cr0n1 register when the valid edge of the ti0n0 pin input is detected and to the cr0n0 register when the valid edge of the ti0n1 pin input is detected. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 190 figure 7-28. timing example of free-running timer mode (cr0n0 register: capture register, cr0 n1 register: capture register) (2/2) (b) toc0n = 13h, prm0n = c0h, crc0n = 05h, tmc0n = 04h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n1) capture register (cr0n0) capture interrupt (inttm0n0) capture trigger input (ti0n0) capture register (cr0n1) capture interrupt (inttm0n1) 01 l m p s n o r q t 00 0000h 0000h lmn o pq r s t l l this is an application example where both the edges of the ti0n1 pin are detect ed and the count value is captured to the cr0n0 register in the free-running timer mode. when both the cr0n0 and cr0n1 registers are used as capt ure registers and when the valid edge of only the ti0n1 pin is to be detected, the count val ue cannot be captured to the cr0n1 register. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 191 figure 7-29. example of register setti ngs in free-running timer mode (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 0000010/10 tmc0n3 tmc0n2 tmc0n1 ovf0n free-running timer mode 0: inverts to0n pin output on match between cr0n0 and cr0n1. 1: inverts to0n pin output on match between cr0n0 and cr0n1 and valid edge of ti0n0 pin. (b) capture/compare contro l register 0n (crc0n) 000000/10/10/1 crc0n2 crc0n1 crc0n0 0: cr0n0 used as compare register 1: cr0n0 used as capture register 0: cr0n1 used as compare register 1: cr0n1 used as capture register 0: ti0n1 pin is used as capture trigger of cr0n0. 1: reverse phase of ti0n0 pin is used as capture trigger of cr0n0. (c) 16-bit timer output control register 0n (toc0n) 0 0 0 0/1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 0: disables to0n output 1: enables to0n output 00: does not invert to0n output on match between tm0n and cr0n0/cr0n1. 01: inverts to0n output on match between tm0n and cr0n0. 10: inverts to0n output on match between tm0n and cr0n1. 11: inverts to0n output on match between tm0n and cr0n0/cr0n1. specifies initial value of to0n output f/f 0/1 0/1 0/1 remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 192 figure 7-29. example of register setti ngs in free-running timer mode (2/2) (d) prescaler mode register 0n (prm0n) 0/1 0/1 0/1 0/1 0 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 count clock selection (setting ti0n0 valid edge is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting prohibited when crc0n1 = 1) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) when this register is used as a compare register and when its value matches the count value of the tm0n register, an interrupt signal (inttm0n0) is generat ed. the count value of t he tm0n register is not cleared. to use this register as a capture register, select ei ther the ti0n0 or ti0n1 pin i nput as a capture trigger. when the valid edge of the capture trig ger is detected, the count value of the tm0n register is stored in the cr0n0 register. (g) 16-bit capture/compare register 0n1 (cr0n1) when this register is used as a compare register and when its value matches the count value of the tm0n register, an interrupt signal (inttm0n1) is generat ed. the count value of t he tm0n register is not cleared. when this register is used as a capture register, t he ti0n0 pin input is used as a capture trigger. when the valid edge of the capture trigger is detected, the count value of the tm0n register is stored in the cr0n1 register. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 193 figure 7-30. example of software pr ocessing in free-running timer mode ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) timer output control bits (toe0n, toc0n4, toc0n1) to0n pin output m 01 n n n n m m m 00 <1> <2> 00 n tmc0n3, tmc0n2 bits = 0, 1 register initial setting prm0n register, crc0n register, toc0n register note , cr0n0/cr0n1 register, tmc0n.tmc0n1 bit, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits to 01. starts count operation start <1> count operation start flow tmc0n3, tmc0n2 bits = 0, 0 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <2> count operation stop flow note care must be exercised when setting the toc0n register. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . because the ti0n0 pin functions alternately as the to0n pin, the timer output (to0n pin) cannot be used if the toc0n register is captured by the valid edge of the ti0n0 pin. be sure to clear the toc0n register to 00h. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 194 7.4.6 ppg output operation a rectangular wave having a pulse width set in advance by the cr0n1 register is out put from the to0n pin as a ppg (programmable pulse generator) signal during a cycle se t by the cr0n0 register when the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits are set to 11 (clear & start upon a ma tch between the tm0n register and the cr0n0 register). the pulse cycle and duty factor of the pulse generated as the ppg output are as follows. ? pulse cycle: (set value of the cr0n0 register + 1) count clock cycle ? duty: (set value of the cr0n1 register + 1)/(set value of the cr0n0 register + 1) caution to change the duty factor (value of the cr0 n1 register) during operat ion, see 7.5.1 rewriting cr0n1 register durin g tm0n operation. remarks 1. for the alternate-function pin (to0n) settings, see table 4-15 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 and inttm0n1 interrupts, see chapter 16 interrupt/exception processing function . figure 7-31. block diagram of ppg output operation 16-bit counter (tm0n) clear output controller compare register (cr0n1) match signal to0n pin match signal interrupt signal (inttm0n0) interrupt signal (inttm0n1) compare register (cr0n0) operable bits tmc0n3, tmc0n2 count clock remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 195 figure 7-32. example of register settings for ppg output operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001100 tmc0n3 tmc0n2 ovf0n clears and starts on match between tm0n and cr0n0. (b) capture/compare contro l register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr0n0 used as compare register cr0n1 used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 0 0 1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n output 11: inverts to0n output on match between tm0n and cr0n0/cr0n1. 00: disables one-shot pulse output specifies initial value of to0n output f/f 0/1 1 1 (d) prescaler mode register 0n (prm0n) 00000 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock 0 0/1 0/1 (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) an interrupt signal (inttm0n0) is generated when the value of this register matches the count value of the tm0n register. (g) 16-bit capture/compare register 0n1 (cr0n1) an interrupt signal (inttm0n1) is generated when the value of this register matches the count value of the tm0n register. the count value of the tm0n register is not cleared. caution set values to the cr0n0 and cr0n1 registers such that the condition 0000h cr0n1 < cr0n0 ffffh is satisfied. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 196 figure 7-33. example of software pr ocessing for ppg output operation tm0n register 0000h operable bits (tmc0n3, tmc0n2) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) timer output control bits (toe0n, toc0n4, toc0n1) to0n pin output m 11 m m m n n n 00 <1> n + 1 <2> 00 n tmc0n3, tmc0n2 bits = 11 register initial setting prm0n register, crc0n register, toc0n register note , cr0n0, cr0n1 registers, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits. starts count operation start <1> count operation start flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <2> count operation stop flow n + 1 n + 1 m + 1 m + 1 m + 1 note care must be exercised when setting the toc0n register. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remarks 1. ppg pulse cycle = (m + 1) count clock cycle ppg duty = (n + 1)/(m + 1) 2. n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 197 7.4.7 one-shot pulse output operation a one-shot pulse can be output by setting the tmc0n.tm c0n3 and tmc0n.tmc0n2 bits to 01 (free-running timer mode) or to 10 (clear & start mode entered by the ti0n0 pin valid edge) and setting the toc0n.ospe0n bit to 1. when the toc0n.ospt0n is set to 1 or when the valid edg e is input to the ti0n0 pin during timer operation, a pulse of the difference between the va lues of the cr0n0 and cr0n1 registers is output only once from the to0n pin. caution do not input the trigger again (setting ospt0n to 1 or detecting the valid edge of the ti0n0 pin) while the one-shot pulse is output. to output th e one-shot pulse again, gene rate the trigger after the current one-shot pulse output has completed. remarks 1. for the alternate-function pin (to0n) settings, see table 4-15 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 and inttm0n1 interrupts, see chapter 16 interrupt/exception processing function . figure 7-34. block diagram of on e-shot pulse output operation 16-bit counter (tm0n) output controller compare register (cr0n1) match signal to0n pin match signal interrupt signal (inttm0n0) interrupt signal (inttm0n1) compare register (cr0n0) operable bits tmc0n3, tmc0n2 count clock ti0n0 edge detection ospt0n bit ospe0n bit clear remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 198 figure 7-35. example of register settings for one-shot pulse output operation (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 00000/10/100 tmc0n3 tmc0n2 tmc0n1 ovf0n 01: free running timer mode 10: clear and start mode by valid edge of ti0n0 pin. (b) capture/compare contro l register 0n (crc0n) 00000000 crc0n2 crc0n1 crc0n0 cr0n0 used as compare register cr0n1 used as compare register (c) 16-bit timer output control register 0n (toc0n) 0 0/1 1 1 0/1 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n pin output inverts to0n output on match between tm0n and cr0n0/cr0n1. specifies initial value of to0n pin output enables one-shot pulse output software trigger is generated by writing 1 to this bit (operation is not affected even if 0 is written to it). 0/1 1 1 (d) prescaler mode register 0n (prm0n) 00000 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 selects count clock 0 0/1 0/1 remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 199 figure 7-35. example of register settings for one-shot pulse output operation (2/2) (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) this register is used as a compare register when a one-shot pulse is output. when the value of the tm0n register matches that of the cr0n0 register, an interrupt signal (inttm0n0) is generated and the output level of the to0n pin is inverted. (g) 16-bit capture/compare register 0n1 (cr0n1) this register is used as a compare register when a one-shot pulse is output. when the value of the tm0n register matches that of the cr0n1 register, an interrupt signal (inttm0n1) is generated and the output level of the to0n pin is inverted. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 200 figure 7-36. example of software processing for one-shot pulse output operation (1/2) ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) one-shot pulse enable bit (ospen) one-shot pulse trigger bit (osptn) one-shot pulse trigger input (ti0n0 pin) overflow plug (ovf0n) compare register (cr0n0) compare match interrupt (inttm0n0) compare register (cr0n1) compare match interrupt (inttm0n1) to0n pin output to0n output control bits (toe0n, toc0n4, toc0n1) n m n ? m n ? m 01 or 10 00 00 n n n m m m m + 1 m + 1 <1> <2> <2> <3> to0n output level is not inverted because no one- shot trigger is input. ? time from when the one-shot pulse trigger is input until the one-shot pulse is output = (m + 1) count clock cycle ? one-shot pulse output active level width = (n ? m) count clock cycle remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 201 figure 7-36. example of software processing for one-shot pulse output operation (2/2) tmc0n3, tmc0n2 bits = 01 or 10 register initial setting prm0n register, crc0n register, toc0n register note , cr0n0, cr0n1 registers, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits. starts count operation start <1> count operation start flow <2> one-shot trigger input flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <3> count operation stop flow toc0n.ospt0n bit = 1 or edge input to ti0n0 pin write the same value to the bits other than the ospt0n bit. note care must be exercised when setting the toc0n register. for details, see 7.3 (3) 16-bit timer output control register 0n (toc0n) . remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 202 7.4.8 pulse width measurement operation the tm0n register can be used to m easure the pulse width of the signal input to the ti0n0 and ti0n1 pins. measurement can be accomplished by oper ating the 16-bit timer/event counter 0n in the free-running timer mode or by restarting the timer in synchronizati on with the signal input to the ti0n0 pin. when an interrupt is generated, read the value of the va lid capture register and measure the pulse width. check the tmc0n.ovf0n flag. if it is set (to 1), clear it to 0 by software. figure 7-37. block di agram of pulse width measureme nt (free-running timer mode) 16-bit counter (tm0n) capture register (cr0n0) capture signal capture signal interrupt signal (inttm0n1) interrupt signal (inttm0n0) capture register (cr0n1) operable bits tmc0n3, tmc0n2 count clock edge detection ti0n0 pin edge detection ti0n1 pin selector remark n = 0 to 3 figure 7-38. block diagram of pulse width measurement (clear & start mode entered by ti0n0 pin valid edge input) 16-bit counter (tm0n) capture register (cr0n0) capture signal capture signal interrupt signal (inttm0n1) interrupt signal (inttm0n0) capture register (cr0n1) operable bits tmc0n3, tmc0n2 count clock edge detection ti0n0 pin edge detection ti0n1 pin clear selector remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 203 a pulse width can be measured in the following three ways. ? measuring the pulse width by using two input signals of the ti0n0 and ti0n1 pins (free-running timer mode) ? measuring the pulse width by using one input signal of the ti0n0 pin (free-running timer mode) ? measuring the pulse width by using one input signal of the ti0n0 pin (clear & start mode entered by the ti0n0 pin valid edge input) remarks 1. for the alternate-function pin (to0n) settings, see table 4-15 settings when port pins are used for alternate functions . 2. for enabling the inttm0n0 and inttm0n1 interrupts, see chapter 16 interrupt/exception processing function . (1) measuring the pulse width by using two input signals of the ti0n0 and ti0n1 pins (free-running timer mode) set the free-running timer mode (the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits = 01). when the valid edge of the ti0n0 pin is detected, th e count value of the tm0n register is c aptured to the cr0n1 register. when the valid edge of the ti0n1 pin is detected, the count value of the tm0n register is captured to the cr0n0 register. specify detection of both the edg es of the ti0n0 and ti0n1 pins. by this measurement method, the prev ious count value is subtracted fr om the count value captured by the edge of each input signal. therefore, save the previously captured val ue to a separate register in advance. if an overflow occurs, the value becomes negative if the previously captured value is simply subtracted from the current captured value and, therefor e, a borrow occurs (the psw.cy bit is set to 1). if this happens, ignore cy and take the calculated value as the pulse width. in addition, clear the tmc0n.ovf0n bit to 0. figure 7-39. timing example of pulse width measurement (1) ? tmc0n = 04h, prm0n = f0h, crc0n = 05h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n0) capture register (cr0n1) capture interrupt (inttm0n1) capture trigger input (ti0n1) capture register (cr0n0) capture interrupt (inttm0n0) overflow flag (ovf0n) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h abc d e 0000h mn s p q remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 204 (2) measuring the pulse width by using one input si gnal of the ti0n0 pin (free-running timer mode) set the free-running timer mode (the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits = 01). the count value of the tm0n register is captured to the cr0 n0 register in the phase reverse to the valid edge detected on the ti0n0 pin. when the valid edge of the ti0n0 pin is detected, the count value of the tm0n register is captured to the cr0n1 register. by this measurement method, values are stored in se parate capture registers when a width from one edge to another is measured. therefor e, the capture values do not have to be saved. by s ubtracting the value of one capture register from that of a nother, a high-level width, low-level width, and cycle are calculated. if an overflow occurs, the value becomes negative if o ne captured value is simply subtracted from another and, therefore, a borrow occurs (the psw.cy bit is set to 1). if this happens, ignore cy and take the calculated value as the pulse width. in addition, clear the tmc0n.ovf0n bit to 0. figure 7-40. timing example of pulse width measurement (2) ? tmc0n = 04h, prm0n = 10h, crc0n = 07h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n0) capture register (cr0n0) capture register (cr0n1) capture interrupt (inttm0n1) overflow flag (ovf0n) capture trigger input (ti0n1) capture interrupt (inttm0n0) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h l l abc d e 0000h mn s p q remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 205 (3) measuring the pulse width by using one input signal of the ti0n0 pin (clear & start mode entered by the ti0n0 pin valid edge input) set the clear & start mode entered by the ti0n0 pi n valid edge (the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits = 10). the count value of the tm0n register is captured to the cr0n0 register in the phase reverse to the valid edge of the ti0n0 pin, and the count value of the tm0n register is ca ptured to the cr0n1 register and the tm0n register is cleared (0000h) when the valid edge of the ti0n0 pin is detected. therefore, a cycle is stored in the cr0n1 register if t he tm0n register does not overflow. if an overflow occurs, take the value that results from adding 10000h to the value stored in the cr0n1 register as a cycle. clear the tmc0n.ovf0n bit to 0. figure 7-41. timing example of pulse width measurement (3) ? tmc0n = 08h, prm0n = 10h, crc0n = 07h ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n0) capture register (cr0n0) capture register (cr0n1) capture interrupt (inttm0n1) overflow flag (ovf0n) capture trigger input (ti0n1) capture interrupt (inttm0n0) 10 <1> <2> <3> <3> <3> <3> <2> <2> <2> <1> <1> <1> m a b cd n s p q 00 00 0 write clear 0000h l l abc d 0000h mn s p q <1> pulse cycle = (10000h number of times ovf0n bit is set to 1 + captured value of the cr0n1 register) count clock cycle <2> high-level pulse width = (10000h number of times ovf0n bit is set to 1 + captured value of the cr0n0 register) count clock cycle <3> low-level pulse width = (pulse cycle ? high-level pulse width) remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 206 figure 7-42. example of register setti ngs for pulse width measurement (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 00000/10/100 tmc0n3 tmc0n2 ovf0n 01: free running timer mode 10: clear and start mode entered by valid edge of ti0n0 pin. (b) capture/compare contro l register 0n (crc0n) 0000010/11 crc0n2 crc0n1 crc0n0 1: cr0n0 used as capture register 1: cr0n1 used as capture register 0: ti0n1 pin is used as capture trigger of cr0n0. 1: reverse phase of ti0n0 pin is used as capture trigger of cr0n0. (c) 16-bit timer output control register 0n (toc0n) 00000 lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n 000 (d) prescaler mode register 0n (prm0n) selects count clock (setting valid edge of ti0n0 is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting when crc0n1 = 1 is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0/1 0/1 0/1 0/1 0 prm0n1 prm0n0 es1n1 es1n0 es0n1 es0n0 0 0/1 0/1 remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 207 figure 7-42. example of register setti ngs for pulse width measurement (2/2) (e) 16-bit timer counter 0n (tm0n) by reading the tm0n register, the count value can be read. (f) 16-bit capture/compare register 0n0 (cr0n0) this register is used as a capture register. eit her the ti0n0 or ti0n1 pin is selected as a capture trigger. when a specified edge of t he capture trigger is det ected, the count value of the tm0n register is stored in the cr0n0 register. (g) 16-bit capture/compare register 0n1 (cr0n1) this register is used as a capture register. the signal input to the ti0n0 pin is used as a capture trigger. when the capture trigger is detected, the count value of the tm0n register is stored in the cr0n1 register. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 208 figure 7-43. example of software proce ssing for pulse width measurement (1/2) (a) example of free-running timer mode ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture trigger input (ti0n0) capture register (cr0n1) capture interrupt (inttm0n1) capture trigger input (ti0n1) capture register (cr0n0) capture interrupt (inttm0n0) 01 d 00 d 00 d 01 d 01 d 02 d 02 d 03 d 03 d 04 d 04 d 10 d 10 d 11 d 11 d 12 d 12 d 13 d 13 00 00 0000h 0000h <1> <2> <2> <2> <2> <2> <2> <2> <2> <2> <3> (b) example of clear & start mode entered by ti0n0 pin valid edge ffffh tm0n register 0000h operable bits (tmc0n3, tmc0n2) capture & count clear input (ti0n0) capture register (cr0n0) capture interrupt (inttm0n0) capture register (cr0n1) capture interrupt (inttm0n1) 10 d 0 l d 0 d 1 d 1 d 2 d 2 d 3 d 3 d 4 d 4 d 5 d 5 d 6 d 6 d 7 d 7 d 8 d 8 00 00 0000h 0000h <1> <2> <2> <2> <2> <2> <2> <2> <2> <3> <2> remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 209 figure 7-43. example of software proce ssing for pulse width measurement (2/2) <2> capture trigger input flow edge detection of ti0n0, ti0n1 pins calculated pulse width from capture value stores count value to cr0n0, cr0n1 registers. generates capture interrupt note . tmc0n3, tmc0n2 bits = 01 or 10 register initial setting prm0n register, crc0n register, port setting initial setting of these registers is performed before setting the tmc0n3 and tmc0n2 bits. starts count operation start <1> count operation start flow tmc0n3, tmc0n2 bits = 00 the counter is initialized and counting is stopped by clearing the tmc0n3 and tmc0n2 bits to 00. stop <3> count operation stop flow note the capture interrupt signal (inttm0n0) is not ge nerated when the reverse-ph ase edge of the ti0n0 pin input is selected to the valid edge of the cr0n0 register. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 210 7.5 special use of tm0n 7.5.1 rewriting cr0n1 register during tm0n operation in principle, rewriting the cr0n0 and cr0n1 register s of the v850es/pm1 when they are used as compare registers is prohibited while the tm 0n register is operating (tmc0n.tmc 0n3 and tmc0n.tmc0n2 bits = other than 00). however, the value of the cr0n1 register can be changed, even while the tm0n register is operating, using the following procedure if the cr0n1 register is used for ppg output and the duty fa ctor is changed (change the value of the cr0n1 register immediately after its value matches th e value of the tm0n register. if the value of the cr0n1 register is changed immediately before its value matc hes the tm0n register, an unexpected operation may be performed). procedure for changing value of the cr0n1 register <1> disable interrupt inttm0n1 (tmic0n1.tmmk0n1 bit = 1). <2> disable reversal of the timer output when the value of the tm0n register matches that of the cr0n1 register (toc0n.toc0n4 bit = 0). <3> change the value of the cr0n1 register. <4> wait for one cycle of the count clock of the tm0n register. <5> enable reversal of the timer output when the value of the tm0n register matches that of the cr0n1 register (toc0n.toc0n4 bit = 1). <6> clear the interrupt flag of inttm0n1 to 0 (tmic0n1.tmif0n1 bit = 0). <7> enable interrupt inttm0n1 (tmic0n1.tmmk0n1 bit = 0). remark for the tmic0n1 register, see chapter 16 interrupt/exception processing function . 7.5.2 setting lvs0n and lvr0n bits (1) usage of the lvs0n and lvr0n bits the toc0n.lvs0n and toc0n.lvr0n bits are used to set the default value of the to0n pin output and to invert the timer output without enabl ing the timer operation (tmc0n.tmc0 n3 and tmc0n.tmc0n2 bits = 00). clear the lvs0n and lvr0n bits to 00 (default value: lo w-level output) when software control is unnecessary. lvs0n bit lvr0n bit timer output status 0 0 not changed (low-level output) 0 1 cleared (low-level output) 1 0 set (high-level output) 1 1 setting prohibited remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 211 (2) setting the lvs0n and lvr0n bits set the lvs0n and lvr0n bits using the following procedure. figure 7-44. example of flow for setting lvs0n and lvr0n bits setting toc0n.ospe0n, toc0n4, toc0n1 bits setting toc0n.toe0n bit setting toc0n.lvs0n, lvr0n bits setting tmc0n.tmc0n3, tmc0n2 bits <3> enabling timer operation <2> setting of timer output f/f <1> setting of timer output operation caution be sure to set the lvs0n and lvr0n bits following steps <1>, <2>, and <3> above. step <2> can be performed after <1> and before <3>. remark n = 0 to 3 figure 7-45. timing example of lvr0n and lvs0n bits toc0n.lvs0n bit toc0n.lvr0n bit operable bits (tmc0n3, tmc0n2) to0n pin output inttm0n0 signal <1> 00 <2> <1> <3> <4> <4> <4> 01, 10, or 11 <1> the to0n pin output goes high wh en the lvs0n and lvr0n bits = 10. <2> the to0n pin output goes low when the lvs0n an d lvr0n bits = 01 (the pin output remains unchanged from the high level even if the lvs0n and lvr0n bits are cleared to 00). <3> the timer starts operating when the tmc0n3 and tm c0n2 bits are set to 01, 10, or 11. because the lvs0n and lvr0n bits were set to 10 before the operat ion was started, the to0n pin output starts from the high level. after the timer starts operating, se tting the lvs0n and lvr0n bits is prohibited until the tmc0n3 and tmc0n2 bits = 00 (disabling the timer operation). <4> the output level of the to0n pi n is inverted each time an interrupt signal (inttm0n0) is generated. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 212 7.6 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because the tm0n register is started asynchronously to the count pulse. figure 7-46. start timing of tm0n register 0000h timer start 0001h 0002h 0003h 0004h count pulse tm0n count value remark n = 0 to 3 (2) setting 16-bit timer capture/compare register (in the mode in which clear & start occurs upon match between tm0n register and cr0n0 register) set the cr0n0 register to a value other than 0000h (whe n using this register as an event counter, one-pulse count operation is not possible). (3) data hold timing of capture register <1> if the valid edge of the ti0n0 pin is input while th e cr0n1 register is being read, the cr0n1 register performs the capture operation. at this time, the captured value is guaranteed but the read value is not. however, an interrupt request signal (inttm0n1) is gener ated as a result of detec tion of the valid edge. figure 7-47. data hold timing of capture register n n + 1 n + 2 x n+ 1 m m + 1 m + 2 count pulse tm0n count value edge input inttm0n1 cr0n1 capture value capture read signal capture operation is performed but read value is not guaranteed capture operation remark n = 0 to 3 <2> the values of the cr0n0 and cr0n1 registers are not guaranteed after 16-bit timer/event counter 0n has stopped. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 213 (4) setting valid edge before setting the valid edge of the ti0n0 and ti0n1 pins, stop the timer operation by clearing the tmc0n.tmc0n2 and tmc0n.tmc0n3 bits to 00. set the valid edge by using the prm0n.es0n0, prm0n.es0n1, prm0n.es1n0, and prm0n. es1n1 bits. the ti0n0 and ti0n1 pins function alte rnately as the p98/a8 to p915/a 15 pins. to use the ti0n0 and ti0n1 pins, select the timer input function by using the pm c9m and pfc9m bits before enabling the timer operation with the tmc0n register. if the pmc9m and pfc9m bits are manipulated after the timer operation, the edge cannot be detected correctly. remark n = 0 to 3, m = 8 to 15 (5) re-triggering one-shot pulse (a) one-shot pulse output by software (tm00 to tm03) when a one-shot pulse is output, do not set the toc 0n.ospt0n bit (1). to output the one-shot pulse again, wait until the current one-s hot pulse output is completed. (b) one-shot pulse output with external trigger if an external trigger is generated again while a one- shot pulse is being output, the timer is cleared and started. (c) one-shot pulse output function when using the one-shot pulse output of timer 0 with a software trigger, do not change the level of the ti0n0 pin or its alternat e function port pin. because the external trigger is effective even in th is case, the timer is cleared and started even with the ti0n0 pin or its alternate function port pin level, resulting in the output of a pulse at an undesired timing. with the v850es/pm1, the internal ti0n0 signal level is fixed to lo w level when a function other than ?timer input function? is selected by using the pmc9 and pfc9 registers. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 214 (6) operation of ovf0n flag (a) setting of ovf0n flag the ovf0n flag is set to 1 in the following case. select either the mode in which clear & start o ccurs upon match between the tm0n register and the cr0n0 register, the mode in which clear & start occu rs upon detection of the valid edge of the ti0n0 register, or the free-running mode. set the cr0n0 register to ffffh when the tm0n register counts up from ffffh to 0000h figure 7-48. operation timing of ovf0n flag fffeh ffffh ffffh 0000h 0001h count pulse tm0n inttm0n0 ovf0n cr0n0 remark n = 0 to 3 (b) clearing of ovf0n flag after the tm0n register overflows, clearing ovf0n flag is invalid and set again even if the ovf0n flag is cleared before the next count clock is counte d (before tm0n register becomes 0001h). remark n = 0 to 3 (7) timer operation (a) cr0n1 register capture even if the tm0n register is read, the read data cannot be captured into the cr0n1 register. (b) ti0n0, ti0n1 pin acknowledgment regardless of the cpu?s operation mode, if the timer is stopped, signals input to the ti0n0 and ti0n1 pins are not acknowledged. (c) one-shot pulse output (tm00 to tm03) one-shot pulse output operates norma lly in either the free-running mode or the mode in which clear & start occurs on the valid edge of the ti0n0 pin. bec ause no overflow occurs in the mode in which clear & start occurs upon match between the tm 0n register and the cr0n0 regist er, one-shot pulse output is not possible. remark n = 0 to 3
chapter 7 16-bit timer/event counters 00 to 03 user?s manual u16237ej3v0ud 215 (8) capture operation (a) if valid edge of ti0n0 pin is specified for count clock if the valid edge of the ti0n0 pin is s pecified for the count clock, the c apture register that specified the ti0n0 pin as the trigger does not operate normally. (b) if both rising and falling edges are specified as valid edge of ti0n0 pin if both the rising and falling edges are specified as th e valid edge of the ti0n0 pin and the capture trigger of the cr0n0 register is specified as the inverse ed ge of the ti0n0 valid edge, t he capture operation is not performed. (c) to ensure that signals from ti0n1 and ti0n0 pins are correctly captured for the capture trigger to capture the signals from the ti0n1 and ti0n0 pins correctly, a pulse longer than two of the count clocks selected by the prm0n register is required. (d) interrupt request input although a capture operation is per formed at the falling edge of the count clock, an interrupt request signal (inttm0n0, inttm0n1) is generated at t he rising edge of the next count clock. (e) note when crc0n.crc0n1 bit is set to 1 when the count value of the tm0n register is captured to the cr0n0 register in the phase reverse to the signal input to the ti0n0 pin, the interrupt request signal (inttm0n0) is not generated after the count value is captured. if the valid edge is detected on the ti0n1 pin during this operation, the capture operation is not performed but the inttm0n0 signal is generated as an external interrupt signal. mask the inttm0n0 signal when the external interrupt is not used. remark n = 0 to 3 (9) compare operation when set in the compare mode, the cr0n0 and cr0n1 re gisters do not perform capt ure operation even if a capture trigger is input. remark n = 0 to 3 (10) edge detection the sampling clock for noise elimination differs dependin g on whether the valid edge of the ti0n0 pin is used for the count clock or as a capture trigger. in the former case, sampling is performed using f xx , and in the latter case, sampling is performed using the count clock selected by the prm0n regi ster. the first capture operation does not start until the valid edges are sampled and two valid leve ls are detected, thus eliminating noise with a short pulse width. remarks 1. f xx : main clock frequency 2. n = 0 to 3
user?s manual u16237ej3v0ud 216 chapter 8 16-bit timer/even t counters 10 and 11 8.1 features 16-bit timer/event counters 10 and 11 can perform the following operations. ? interval timer function ? pwm output ? external signal cycle measurement 8.2 function overview ? 16-bit timer/counter ? capture/compare common registers: 2 2 channels ? interrupt request sources ? capture/match interrupt requests: 2 2 channels ? overflow interrupt requests: 1 2 channels ? timer/counter count clock sources: 2 (selection of external pulse input or internal system clock division) ? either free-running mode or overflow stop mode can be selected as the operation mode when the timer/counter overflows ? timer/counter can be cleared by a match of the timer/counter and a compare register ? external pulse outputs: 1 2 channels
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 217 8.3 configuration table 8-1. configuration of 16-bit timer/event counters 10, 11 timer count clock register read/write generated interrupt signal capture trigger timer output s/r tm10 read intovf10 ? ? cc100 read/write intcc100 intp100 to10 (s) cc101 read/write intcc101 intp101 to10 (r) tm11 read intovf11 ? ? cc110 read/write intcc110 intp110 to11 (s) tm10, tm11 f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256 cc111 read/write intcc111 intp111 to11 (r) remark f xx : internal system clock s/r: set/reset figure 8-1. block diagram of 16-bit timer/event counter 1n r note q sq tm1n (16 bits) cc1n0 cc1n1 intovf1n intcc1n0 intp1n1 f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx ti1n/intp1n0/tclr1n intcc1n1 to1n clear & start selector selector f xx note reset priority remarks 1. n = 0, 1 2. f xx : main clock frequency
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 218 (1) 16-bit timer counters 10 and 11 (tm10 and tm11) the tm1n register functions as a 16-bit free-running ti mer or as an event counter for an external signal. besides being used for cycle measurement, tm1n c an be used for pulse output (n = 0, 1). the tm1n register is read-only, in 16-bit units. cautions 1. the tm1n register can only be read. if the tm1n register is written, the subsequent operation is undefined. 2. if the tmc1n0.tm1caen bit is cleared (0), a reset is performed asynchronously. 3. when the main clock is stopped and the cpu is operating on the subclock, do not access the tm1n register using an access method that causes a wait. for details, see 3.4.8 (2). tm11 fffff610h 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 tm10 fffff600h 0000h address after reset 0 (a) selection of count clock the tm1n register performs the count- up operation of an internal count clock or external count clock. timer start and stop are controlled by the tmc1n0.tm1cen bit (n = 0, 1). the internal or external count clock is selected by the tmc1n1.eti1n bit (n = 0, 1). (i) selection of the external count clock the tm1n register operates as an event counter. when the tmc1n1.eti1n bit is set (1), the tm1n regist er counts the valid edges of the external clock input (ti1n), synchronized with t he internal count clock. the vali d edge is specified by the ses1n register (n = 0, 1). caution when the intp1n0/ti1n/tclr1n pin is u sed as ti1n (external clock input pin), disable the intp1n0 pin interrupt and set the cc1n0 register to compare mode (n = 0, 1).
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 219 (ii) selection of the internal count clock the tm1n register operates as a free-running timer. when the internal clock is specified as the count clock by the tmc1n1 register, tm1n is counted up for each input clock cycle specified by the tmc1n0. cs1n0 to tmc1n0.cs1n2 bits (n = 0, 1). division by the prescaler can be selected for the count clock from among f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, and f xx /256 by the tmc1n0 register (f xx : internal system clock). an overflow interrupt can be generated if the timer overflows. also, the timer can be stopped following an overflow by setting the tmc1n1.ost1n bit (1). caution the count clock cannot be ch anged while the timer is operating. (b) conditions when tm1n register becomes 0000h. (i) asynchronous reset ? tmc1n0.tm1caen bit = 0 ? reset input (ii) synchronous reset ? tmc1n0.tm1cen bit = 0 ? the cc1n0 register is used as a compare regi ster, and the tm1n and cc1n0 registers match when clearing the tm1n register is enabled (tmc1n1.cclr1n bit = 1)
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 220 (2) 16-bit timer capture/compar e registers 1n0 and 1n1 (cc1n0 and cc1n1) (n = 0, 1) the ccin0 and cc1n1 registers are 16-bit registers. they can be used as capture registers or com pare registers according to the tmc1n1.cms1n0 and tmc1n1.cms1n1 bit specifications (n = 0, 1). these registers can be read or written in 16-bit units . (however, write operations can only be performed in compare mode.) reset sets these registers to 0000h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the cc1n0 and cc1n1 registers using an access method that causes a wait. for details, see 3.4.8 (2). cc1n1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cc1n0 crc100 fffff602h, crc110 fffff612h crc101 fffff604h, crc111 fffff614h 0000h 0000h address after reset 0 remark n = 0, 1 (a) setting these registers as capture register s (tmc1n1.cms1n0 and tmc1n1.cms1n1 = 0) when these registers are set as capture registers, the valid edges of the corresponding external interrupt signals intp1n0 and intp1n1 are detected as capture triggers. the timer tm1n is synchronized with the capture trigger, and the value of tm1n is latched in the cc1n0 and cc1n1 regist ers (capture operation). the valid edge of the intp1n0 pin is specified (rising, falling, or both rising and falling edges) according to the ses1n.ies1n01 and ses1n.ies1n0 0 bits, and the valid edge of the intp1n1 pin is specified according to the ies1n11 and ies1n10 bits of the ses1n register (n = 0, 1). the capture operation is performed a synchronously to the count clock. the latched value is held in the capture register until anot her capture operation is performed (n = 0, 1). when the tmc1n0.tm1caen bit is 0, 0000h is read (n = 0, 1). if these registers are specified as c apture registers, an interrupt is gener ated by detecting the valid edge of signals intp1n0 and intp1n1 (n = 0, 1). caution if the capture operation conflicts with the timing of disabling the tm1n register from counting (when the tm1cen bit of the tmc1n0 register = 0), the captured data becomes undefined. in addition, the intcc1n0 and in tcc1n1 interrupts do not occur (n = 0, 1).
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 221 (b) setting these registers as compare register s (tmc1n1.cms1n0 and tmc1n1.cms1n1 = 1) when these registers are set as compare registers, the tm1n register and compare register values are compared for each count clock, and an interrupt is ge nerated by a match. if the tmc1n1.cclr1n bit is set (1), the tm1n value is cleared (0000h) at the same time as a match with the cc1n0 register (it is not cleared (0000h) by a match with the cc1n1 register) (n = 0, 1). compare registers are equipped with a set/reset function. the correspondi ng timer output (to1n) is set or reset, in synchronization with the genera tion of a match signal (n = 0, 1). the interrupt selection source differs accord ing to the function of the selected register. cautions 1. when writing to the cc1n0 and cc1n1 registers, always set the tm1caen bit to 1 first. if the tm1caen bit is 0, the data that is written will be invalid. 2. write to the cc1n0 and cc1n1 registers after setting them as compare registers via tmc1n0 and tmc1n1 register settings. if they are set as capture registers (tmc1n1.cms1n0 and tmc1n1.cms1n1 bits = 0), no data is written even if a write operation is performed to the cc1n0 and cc1n1 registers. 3. when these registers are set as compare registers, th e intp1n0 and intp1n1 pins cannot be used as capture trigger input pins (n = 0, 1).
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 222 8.4 registers (1) 16-bit timer mode control registers 100 and 110 (tmc100 and tmc110) the tmc1n0 registers control the operation of 16-bit timer/event counter 1n (n = 0, 1). these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. be sure to clear bits 3 and 2 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. the tm1caen bit cannot be set at the same time as the other bits. the other bits and the registers of the other tm1n units should a lways be set after the tm1caen bit has been set. also, to use external pins related to the timer function when the 16-bit timer/event counter is used, be sure to set (1) the tm 1caen bit after setting th e external pins to control mode. 2. when conflict occurs betw een an overflow and a tmc1n0 register write, the ovf1n bit value is not guaranteed (n = 0, 1). 3. when the main clock is stopped and the cpu is operating on the subclock, do not access the tmc1n0 register using an access method that causes a wait. for details, see 3.4.8 (2). (1/2) ovf1n no overflow occurred overflow occurred ovf1n 0 1 tm1n register overflow detection tmc1n0 (n = 0, 1) cs1n2 cs1n1 cs1n0 0 0 tm1cen tm1caen 65432<1> after reset: 00h r/w address: tmc100 fffff606h, tmc110 fffff616h when tm1n has counted up from ffffh to 0000h, the ovf1n bit becomes 1 and an overflow interrupt request (intovf1n) is generated at the same time. however, if tm1n is cleared to 0000h after a match at ffffh when the cc1n0 register is set to compare mode (tmc1n1.cms1n0 bit = 1) and clearing is enabled for a match when tm1n and cc1n0 are compared (tmc1n1.cclr1n bit = 1), then tm1n is considered to be cleared and the ovf1n bit does not become 1. also, no intovf1n interrupt is generated. the ovf1n bit retains the value 1 until 0 is written directly or until an asynchronous reset is performed because the tm1caen bit is 0. an interrupt operation due to an overflow is independent of the ovf1n bit, and the interrupt request flag (ovfif1n) for intovf1n is not affected even if the ovf1n bit is manipulated. if an overflow occurs while the ovf1n bit is being read, the flag value changes, and the change is reflected when the next read operation occurs. <7> <0>
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 223 (2/2) the entire tm1n unit is asynchronously reset. the supply of clocks to the tm1n unit stops. clocks are supplied to the tm1n unit. tm1caen 0 internal count clock control f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 cs1n2 0 0 0 0 1 1 1 1 internal count clock selection cs1n1 0 0 1 1 0 0 1 1 cs1n0 0 1 0 1 0 1 0 1 count disabled (stops at 0000h and does not operate). counting operation is performed. tm1cen 0 1 tm1n register operation control when tm1cen = 0, the external pulse output (to1n) becomes inactive (the active level of to1n output is set by the alv1n bit of the tmc1n1 register). ? when the tm1caen bit is set to 0, the tm1n unit can be asynchronously reset. ? when tm1caen = 0, the tm1n unit is in a reset state. therefore, to operate tm1n, the tm1caen bit must be set to 1. ? when the tm1caen bit is changed from 1 to 0, all registers of the tm1n unit are initialized. when the tm1caen bit is set to 1 again, the tm1n unit registers must be set again. 1
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 224 (2) 16-bit timer mode control registers 101 and 111 (tmc101 and tmc111) the tmc1n1 registers control t he operation of 16-bit timer/event counter 1n (n = 0, 1). these registers can be read or wr itten in 8-bit or 1-bit units. reset sets these registers to 20h. cautions 1. the various bits of the tmc1n1 register must not be changed during timer operation. if they are to be changed, they must be changed after clearing the tm1cen bit of the tmc1n0 register to 0. if these bits are overwritten during time r operation, operation cannot be guaranteed (n = 0, 1). 2. if the ento1n and alv1n bits are changed at the same time, a glit ch (spike shaped noise) may be generated in the to1n pin output. ei ther create a circuit configuration that will not malfunction even if a glitch is generated or make sure that the ento1n and alv1n bits do not change at th e same time (n = 0, 1). 3. to1n output is not changed by an external interrupt signal (intp1n0 or intp1n1). to use the to1n signal, specify that the capture/ compare registers ar e compare registers (cms1n0 and cms1n1 bits of tmc1 n1 register = 1) (n = 0, 1). (1/2) ost1n after the overflow, counting continues (free-running mode). after the overflow, the timer maintains the value 0000h, and counting stops (overflow stop mode). ost1n 0 1 setting of operation when tm1n register overflowed tmc1n1 (n = 0, 1) ento1n alv1n eti1n cclr1n eclr1n cms1n1 cms1n0 76 54 32 1 0 after reset: 20h r/w address: tmc101 fffff608h, tmc111 fffff618h when ost1n bit = 1, the tmc1n0.tm1cen bit remains at 1. counting is restarted by writing 1 to the tm1cen bit. external pulse output is disabled. external pulse output is enabled. ento1n 0 1 external pulse output (to1n) enable/disable ? when ento1n bit = 0, output of the alv1n bit inactive level to the to1n pin is fixed. the to1n pin level is not changed even if a match signal from the corresponding compare register is generated. ? when ento1n bit = 1, a compare register match causes to1n output to change. however, if capture mode is set, to1n output does not change. the alv1n bit inactive level is output from the time when timer output is enabled until a match signal is first generated. ? if either cc1n0 or cc1n1 is specified as a capture register, the ento1n bit must be set to 0.
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 225 (2/2) clearing is disabled clearing is enabled (after the clearing, restarts counting) eclr1n 0 1 tm1n register clear enable/disable specification by external clear input (tclr1n) the register operates as a capture register. the register operates as a compare register. cms1n1 0 1 16-bit timer capture/compare register (cc1n1) operation mode selection the register operates as a capture register. the register operates as a compare register. cms1n0 0 1 16-bit timer capture/compare register (cc1n0) operation mode selection clearing is disabled clearing is enabled (if cc1n0 and tm1n match during a compare operation, tm1n is cleared) cclr1n 0 1 tm1n register clear enable/disable specification during compare operation low level high level alv1n 0 1 external pulse output (to1n) active level specification the initial value of the alv1n bit is 1. specifies the input clock (internal). specifies the external clock (ti1n0). eti1n 0 1 count clock external/internal switch specification ? when eti1n bit = 0, the internal count clock can be selected according to the tmc1n0.cs1n2 to tmc1n0.cs1n0 bits. ? when eti1n bit = 1, the valid edge can be selected according to the ses1n.tes1n1 and ses1n.tes1n0 bit specifications. remark a reset takes precedence for the flip-f lop of the to1n output (n = 0, 1).
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 226 (3) valid edge select registers 10 and 11 (ses10 and ses11) these registers specify the valid edg e of an external interrupt request (intp100, intp101, intp110, intp111, ti10, ti11, tclr10, and tclr11) from an external pin. the rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin. each of these registers can be read or written in 8-bit units. reset sets these registers to 00h. caution the various bits of the ses1n register must not be changed during ti mer operation. if they are to be changed, they must be changed after clearing the tmc1n0.tm1cen bit to 0. if the ses1n register is overwritte n during timer opera tion, operation ca nnot be guaranteed. falling edge rising edge setting prohibited both rising and falling edges tes1n1 0 0 1 1 valid edge of ti1n pin tes1n0 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges ces1n1 0 0 1 1 valid edge of tclr1n pin ces1n0 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges ies1n11 0 0 1 1 valid edge of intp1n1 pin ies1n10 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges ies1n01 0 0 1 1 valid edge of intp1n0 pin ies1n00 0 1 0 1 tes1n1 ses1n (n = 0, 1) tes1n0 ces1n1 ces1n0 ies1n11 ies1n10 ies1n01 ies1n00 76 54 32 1 0 after reset: 00h r/w address: ses10 fffff609h, ses11 fffff619h
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 227 8.5 operation (1) count operation 16-bit timer/event counter 1n can function as a 16-bit free- running timer or as an external signal event counter. the setting for the type of operation is specified by the tmc1n0 and tmc1n1 registers (n = 0, 1). when it operates as a free-running ti mer, if the cc1n0 or cc1n1 register and the tm1n register count value match, an interrupt signal is generated and the timer outpu t signal (to1n) can be set or reset. also, a capture operation that holds the tm1n register count value in the cc1n0 or cc1n1 register is performed, in synchronization with the valid edge that was detected from the external interrupt request input pin as an external trigger. the capture value is held until the next capture trigger is generated. caution when using the intp1n0/ti1n0 pin as an extern al clock input pin (ti1n0), be sure to disable the intp1n0 interrupt and set cc1n0 to compare mode (n = 0, 1). figure 8-2. basic operation of 16-bit timer/event counter 0001h 0000h 0002h 0003h fbfeh fbffh 0001h 0002h 0000h tm1n count clock ? count disabled tm1cen 0 ? count start tm1cen 1 ? count start tm1cen 1 remark n = 0, 1
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 228 (2) overflow when the tm1n register has counted the count clock from ffffh to 00 00h, the ovf1n bit of the tmc1n0 register is set (1), and an overflow interrupt (intovf1n) is generated at the same time (n = 0, 1). however, if the cc1n0 register is set to co mpare mode (tmc1n1.cms1n0 bit = 1) and to the value ffffh when match clearing is enabled (tmc1n1.cclr1n bit = 1), then the tm1n register is considered to be cleared and the ovf1n bit is not set (1) when the tm 1n register changes from ffffh to 0000h. also, the overflow interrupt (intovf1n) is not generated. when the tm1n register is changed from ffffh to 0000h because th e tmc1n0.tm1cen bit changes from 1 to 0, the tm1n register is considered to be cleared, bu t the ovf1n bit is not set (1) and no intovf1n interrupt is generated. also, timer operation can be stopped after an overflow by setting the tmc1n1.ost1n bit to 1. when the timer is stopped due to an overflow, the count operation is not restarted until the tm1cen bit is set (1). operation is not affected even if the tm1cen bit is set (1) during a count operation. remark n = 0, 1 figure 8-3. operation after overflow (when ost1n = 1) overflow count start overflow ffffh ffffh tm1n 0 intovf1n ost1n 1 tm1cen 1 tm1cen 1 remark n = 0, 1
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 229 (3) capture operation the tm1n register has two capture/comp are registers. these are the cc1 n0 register and the cc1n1 register. a capture operation or a compare operation is performed according to the settings of both the tmc1n1.cms1n1 and tmc1n1.cms1n0 bits. if the cms 1n1 and cms1n0 bits of the tmc1n1 register are cleared to 0, the register o perates as a capture register. a capture operation that c aptures and holds the tm1n r egister count value asynchronously to the count clock is performed in synchronization with an external trigger. the valid edge that is detected from an external interrupt request input pin (intp1n0 or intp1n1) is used as an external trigger (capture trigger). the tm1n register count value during counting is captured and held in the capture regi ster, in synchronization with that capture trigger signal. the captur e register value is held until the next capture trigger is generated. also, an interrupt request (intcc1n0 or intcc1n1) is generated by intp1n0 or intp1n1 signal input. the valid edge of the capture trigger is se t by valid edge select register n (ses1n). if both the rising and falling edges are set as capture trig gers, the input pulse width from an external source can be measured. also, if only one of the edges is set as the capture trigger, the input pulse cycle can be measured. remark n = 0, 1 figure 8-4. capture operation example (tm11) tm11 0 tm1ce1 intp111 cc111 (capture register) n n (capture trigger) (capture trigger) remarks 1. when the tm1ce1 bit is 0, no capture oper ation is performed even if intp111 is input. 2. valid edge of intp111: rising edge
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 230 figure 8-5. tm11 capture operation e xample (when both edges are specified) tm11 ? count start tm1ce1 1 ? overflow ovf11 1 d0 d1 d2 d0 d1 d2 interrupt request (intp111) (tm11 count values) capture register (cc111) remark d0 to d2: tm11 register count values
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 231 (4) compare operation 16-bit timer/event counter 1n has two 16-bit timer capt ure/compare registers. t hese are the cc1n0 register and the cc1n1 register. a capture oper ation or a compare operation is perf ormed according to the settings of both the tmc1n1.cms1n1 and tmc1n1.cms1n0 bits. if the tmc1n1.cms1n1 and tmc1n1.cms1n0 bits are set to 1, the register operates as a compare register. a compare operation that compares the value that was set in the comp are register and the tm1n register count value is performed. if the tm1n register count value matches the value of t he compare register, which had been set in advance, a match signal is sent to the output controller. the match signal causes the timer output pin (to1n) to change and an interrupt request signal (intcc1nn) to be generated at the same time. if the cc1n0 and cc1n1 registers are cleared to 0000h, t he 0000h after the tm1n register counts up from ffffh to 0000h is judged as a match. in this case, the tm1n register va lue is cleared (0000h) at the next count timing, however, this 0000h is not judged as a match. also, the 0000h when the tm1n register begins counting is not judged as a match. if match clearing is enabled (tmc1n1.cclr1n bit = 1) fo r the cc1n0 register, the tm1n register is cleared when a match with the tm1n register oc curs during a compare operation. remark n = 0, 1 figure 8-6. compare operation example (whe n cclr11 = 1 and cc110 is other than 0000h) 0001h 0000h n n n ? 1 tm11 compare register (cc110) match detection (intcc110) remarks 1. a match is detected immediately after the timer/event counter has counted up and a match detection signal is generated when the timer/event counter counts up next time. 2. n 0000h
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 232 figure 8-7. compare operation example (when cclr11 = 1 and cc110 is 0000h) 0001h 0000h 0000h 0000h ffffh tm11 intovf11 compare register (cc110) match detection (intcc110) remark a match is detected immediately after the timer/ev ent counter has counted up and a match detection signal is generated when the timer/ev ent counter counts up next time.
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 233 (5) external pulse output 16-bit timer/event counter 1n has two timer output pins (to1n). an external pulse output (to1n) is generated when a ma tch of the two compare registers (cc1n0 and cc1n1) and the tm1n register is detected. if a match is detected when the tm1n register count va lue and the cc1n0 register value are compared, the output level of the to1n pin is set. also, if a match is detected when the tm1n register count value and the cc1n1 register value are compared, the output level of the to1n pin is reset. the output level of the to1n pin can be specified by the tmc1n1 register. remark n = 0, 1 table 8-2. to1n output control to1n output eti1n alv1n external pulse output output level 0 0 disable high level 0 1 disable low level 1 0 enable when the cc1n0 register is matched: low level when the cc1n1 register is matched: high level 1 1 enable when the cc1n0 register is matched: high level when the cc1n1 register is matched: low level remark n = 0, 1 figure 8-8. tm11 compare operati on example (set/reset output mode) tm11 register count value 0 ffffh ? count start tm1ce1 1 ? overflow ovf11 1 ? overflow ovf11 1 cc111 cc110 ffffh cc111 cc110 cc110 interrupt request (intcc110) interrupt request (intcc111) to1 pin ento11 1 alv11 1
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 234 8.6 application examples (1) interval timer by setting the tmc1n0 and tmc1n1 registers as shown in figure 8-9, the 16-bit timer/event counter operates as an interval timer that repeatedly generates interrupt requests with the value that was preset in the cc1n0 register as the interval. when the count value of the tm1n regi ster matches the setting value of th e cc1n0 register, the tm1n register is cleared (0000h) and an interrupt request signal (intcc 1n0) is generated at the sa me time that the count operation resumes. remark n = 0, 1 figure 8-9. register settings when 16-bit ti mer/event counter is used as interval timer supply input clocks to internal units enable count operation 0 0/1 0/1 0/1 1 0/1 0/1 1 ost1n ento1n alv1n eti1n cclr1n cms1n1 cms1n0 0/1 0/1 0/1 0/1 0 0 1 1 ovf1n tmc1n0 tmc1n1 cs1n2 cs1n1 cs1n0 tm1cen tm1caen use cc1n0 register as compare register clear tmc1n register due to match with cc1n0 register continue counting after tm1n register overflows eclr1n remarks 1. 0/1: clear to 0 or set to 1 as necessary 2. n = 0, 1
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 235 figure 8-10. interval timer operation timing example 0000h 0001h p 0000h 0001h pp p p p p 0000h 0001h t count start interval time interval time interval time count clock tm1n register cc1n0 register intcc1n0 interrupt clear clear remarks 1. p: setting value of cc1n0 register (0000h to ffffh) t: count clock cycle interval time = (p + 1) t 2. n = 0, 1
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 236 (2) pwm output by setting the tmc1n0 and tmc1n1 registers as shown in figure 8-11, the 16-bit timer/event counter can output a pwm signal, whose frequency is determined according to the setting of the tmc1n0.cs1n2 to tmc1n0.cs1n0 bits with the values that were preset in the cc1n0 and cc1n1 registers determining the intervals. when the count value of the tm1n register matches t he setting value of the cc1n0 register, the to1n output becomes active. then, when the count er value of the tm1n register matc hes the setting value of the cc1n1 register, the to1n output becom es inactive. the tm1n register contin ues counting. when it overflows, its count value is cleared to 0000h, and the register cont inues counting. in this way, a pwm signal whose frequency is determined according to the setting of the cs1n2 to cs1n0 bits can be output. when the setting value of the cc1n0 register and the setting value of the cc1n1 register are the same, the to1n output remains inactive and does not change. the active level of the to1n output can be set by the tmc1n1.alv1n bit. remark n = 0, 1 figure 8-11. register settings when 16-bit ti mer/event counter is used for pwm output supply input clocks to internal units enable count operation 0 1 0/1 0/1 0 0/1 1 1 ost1n ento1n alv1n eti1n cclr1n cms1n1 cms1n0 0/1 0/1 0/1 0/1 0 0 1 1 ovf1n tmc1n0 tmc1n1 cs1n2 cs1n1 cs1n0 tm1cen tm1caen use cc1n0 register as compare register use cc1n1 register as compare register disable clearing of tm1n register due to match with cc1n0 register enable external pulse output (to1n) continue counting after tm1n register overflows eclr1n remarks 1. 0/1: set to 0 or 1 as necessary 2. n = 0, 1
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 237 figure 8-12. pwm output operation timing example 0000h 0001h p ppp p p qqq q q qpq 0000h ffffh 0001h count clock tm1n register cc1n0 register cc1n1 register intcc1n0 interrupt intcc1n1 interrupt to1n (output) count start clear t remarks 1. p: setting value of cc1n0 register (0000h to ffffh) q: setting value of cc1n1 register (0000h to ffffh) p q t: count clock cycle pwm cycle = 65,536 t 65,536 p q duty ? = 2. in this example, the active level of the to1n output is set to the high level. 3. n = 0, 1
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 238 (3) one-shot pulse output by setting the tmc1n0 and tmc1n1 registers as shown in figure 8-13, the 16-bit timer/event counter can output a one-shot pulse from the to1n pin by using the valid edge of the tclr1n pin as an external trigger. the valid edge of the tclr1n pin is selected accord ing to the ses1n.ces1n0 and ses1n.ces1n1 bits. the rising edge, falling edge, or both rising and falling edges can be selected as the valid edge. the tm1n register is cleared and started by setting a va lid edge to the tclr1n pin. to1n output becomes active at the count value set in advance to the cc1n0 r egister. after that, the to1n output becomes inactive at the count value set in advance to cc1n1 register. t he active level of the to1n output can be set by the tmc1n1.alv1n bit. when the setting value of the cc1n0 register and the setting value of the cc1n1 register are the same, the to1n output remains inactive and does not change. the active level of the to1n output can be set by the tmc1n1.alv1n bit. remark n = 0, 1 figure 8-13. register settings when 16-bit timer/ev ent counter is used for one-shot pulse output supply input clocks to internal units enable count operation 1 1 0/1 0/1 0 1 1 1 ost1n ento1n alv1 n eti1n cclr1n eclr1n cms1n1 cms1n0 0/1 0/1 0/1 0/1 0 0 1 1 ovf1n tmc1n0 tmc1n1 cs1n2 cs1n1 cs1n0 tm1 cen tm1 caen use cc1n0 register as compare register use cc1n1 register as compare register disable clearing of tm1n register due to match with cc1n0 register enable external pulse output (to1n) enable clearing of tm1n register by tclr1n input after tm1n register overflows, timer retains value of 0000h and stops counting remarks 1. 0/1: clear to 0 or set to 1 as necessary 2. n = 0, 1
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 239 figure 8-14. one-shot pulse ou tput operation timing example 0000h 0001h p ppp p qqq q q 0000h ffffh count start count stop count clock tm1n register cc1n0 register cc1n1 register intcc1n0 interrupt intcc1n1 interrupt to1n (output) t remarks 1. p: setting value of cc1n0 register (0000h to ffffh) q: setting value of cc1n1 register (0000h to ffffh) p q t: count clock cycle 2. in this example, the valid edge of the tclr1n input is set to the rising edge and the active level of the to1n output is set to the high level. 3. n = 0, 1
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 240 (4) cycle measurement by setting the tmc1n0 and tmc1n1 registers as shown in figure 8-15, the 16-bit timer/event counter can measure the cycle of signals input to the intp1n0 or intp1n1 pin. the valid edge of the intp1n0 pin is selected acco rding to the ses1n.ies1n01 and ses1n.ies1n00 bits, and the valid edge of the intp1n1 pin is selected a ccording to the ses1n.ies1n11 and ses1n.ies1n10 bits. either the rising edge, the falling edge, or both edges can be selected as the valid edges of both pins. if the cc1n0 register is set as a capture register, the va lid edge input of the intp1n0 pin is set as the trigger for capturing the tm1n register value in the cc1n0 re gister. when this value is captured, an intcc1n0 interrupt is generated. similarly, if the cc1n1 register is set as a capture regi ster, the valid edge input of the intp1n1 pin is set as the trigger for capturing the tm1n register value in the cc 1n1 register. when this value is captured, an intcc1n1 interrupt is generated. the cycle of signals input to the intp1n0 pin is calc ulated by obtaining the difference between the tm1n register?s count value (dx) that was captured in the cc1n0 register accordin g to the x-th valid edge input of the intp1n0 pin and the tm1n register?s count value (d(x+1)) that was captured in the cc1n0 register according to the (x+1)-th valid edge input of the intp1n0 pin and mu ltiplying the value of this difference by the cycle of the internal count clock note . the cycle of signals input to the intp1n1 pin is calc ulated by obtaining the difference between the tm1n register?s count value (dx) that was captured in the cc1n1 register accordin g to the x-th valid edge input of the intp1n1 pin and the tm1n register?s count value (d(x+1)) that was captured in the cc1n1 register according to the (x+1)-th valid edge input of the intp1n1 pin and mu ltiplying the value of this difference by the cycle of the internal count clock note . note this calculation assumes that the rising/falling edges are selected. remark n = 0, 1
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 241 figure 8-15. register settings when 16-bit time r/event counter is used for cycle measurement supply input clocks to internal units enable count operation 0 0/1 0/1 0/1 0/1 0/1 0 0 ost1n ento1n alv1n eti1n cclr1n cms1n1 cms1n0 0/1 0/1 0/1 0/1 0 0 1 1 ovf1n tmc1n0 tmc1n1 cs1n2 cs1n1 cs1n0 tm1cen tm1caen use cc1n0 register as capture register (when measuring the cycle of intp1n0 input) use cc1n1 register as capture register (when measuring the cycle of intp1n1 input) continue counting after tm1n register overflows eclr1n remarks 1. 0/1: clear to 0 or set to 1 as necessary 2. n = 0, 1
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 242 figure 8-16. cycle measurement operation timing example 0001h 0000h 0001h 0000h ffffh d0 d1 d2 d3 d3 d2 d1 d0 (d1 ? d0) t (d3 ? d2) t {(10000h ? d1) + d2} t note t count clock tm1n register intp1n0 (input) cc1n0 register intcc1n0 interrupt intovf1n interrupt no overflow overflow occurs no overflow clear count start note when an overflow occurs once. remarks 1. d0 to d3: tm1n register count values t: count clock cycle 2. in this example, the valid edge of the intp1n0 input has been set to both edges (rising and falling). 3. n = 0, 1
chapter 8 16-bit timer/event counters 10 and 11 user?s manual u16237ej3v0ud 243 8.7 cautions various cautions concerning the 16-bit timer/event counter are shown below. (1) if a conflict occurs between the reading of the cc1 n0 register and a capture operation when the cc1n0 register is used in capture mode, an external trigger (intp1n0) valid edge is detected and an interrupt request signal (intcc1n0) is generated, however, the ti mer value is not stored in the cc1n0 register. (2) if a conflict occurs between the reading of the cc1 n1 register and a capture operation when the cc1n1 register is used in capture mode, an external trigger (intp1n1) valid edge is detected and an interrupt request signal (intcc1n1) is generated, however, the ti mer value is not stored in the cc1n1 register. (3) the following bits and registers must not be re written during operation (tmc1n0.tm1cen bit = 1). ? tmc1n0.cs1n2 to tmc1n0.cs1n0 bits ? tmc1n1 register ? ses1n register (4) the tmc1n0.tm1caen bit is a reset signal of 16-bit ti mer/event counter 1n. to use 16-bit timer/level counter 1n, first set (1) the tm1caen bit. (5) the analog noise elimination time + two cycles of the input clock are required to detect the valid edge of the external trigger signal (intp1n0 or in tp1n1) or the external cl ock input (ti1n). therefore, edge detection will not be performed normally for changes that are less than the analog noise elimination time + two cycles of the input clock. only two f xx clocks are necessary for detecting the valid edge of the external clear input (tclr1n). (6) the operation of an interrupt request signal (intcc1n0 or intcc1n1) is automatically determined according to the operating state of the captur e/compare register. when the captur e/compare register is used for a capture operation, the external trigger signal is used for a valid edge detection interrupt. when the capture/compare register is used for a compare operatio n, the external interrupt request signal is used for an interrupt indicating a match with the tm1n register. (7) if the tmc1n1.ento1n and tmc1n1.alv1n bits are changed at the same time, a glitch (spike shaped noise) may be generated in the to1n pin output. either create a circuit configuration that will not malfunction even if a glitch is generated or make sure that the ento 1n and alv1n bits are not changed at the same time. remark n = 0, 1
user?s manual u16237ej3v0ud 244 chapter 9 8-bit timer/even t counters 20 and 21 9.1 function overview 8-bit timer/event counter 2n has the following two modes (n = 0, 1). ? mode using 8-bit timer/event counter alone (individual mode) ? mode using cascade connection (16-bit resolution: cascade connection mode) these two modes are described below. (1) mode using 8-bit timer/event counter alone (individual mode) 8-bit timer/event counter 2n operates as an 8-bit timer/event counter. the following functions can be used. ? interval timer ? external event counter ? square wave output ? pwm output (2) mode using cascade connection (16-bi t resolution: cascade connection mode) tm20 and tm21 can be used as 16-bit timer/event coun ters when they are connected in cascade. the following functions can be used. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square wave output with 16-bit resolution the block diagram of 8-bit timer/event counter 2n is shown next.
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 245 figure 9-1. block diagram of 8-bit timer/event counter 2n match clear ovf ti2n count clock note 1 selector selector internal bus internal bus 3 tcl2n2 tcl2n1 tcl2n0 tm2cen tmc2n6 tmc214 lvs2n lvr2n tmc2n1 toe2n 8-bit timer mode control register 2n (tmc2n) 8-bit timer compare register 2n (cr2n) 8-bit timer counter 2n (tm2n) to2n note 2 inttm2n selector selector invert level s r q inv s r q mask circuit timer clock selection register 2n (tcl2n) notes 1. the count clock is set by the tcl2n register. 2. serial interface clock remark n = 0, 1 9.2 configuration 8-bit timer/event counter 2n consists of the following hardware (n = 0, 1). table 9-1. configuration of 8-bit timer/event counter 2n item configuration timer registers 8-bit timer counters 20, 21 (tm20, tm21) 16-bit timer counter 2 (tm2): on ly when using cascade connection registers 8-bit timer compare registers 20, 21 (cr20, cr21) 16-bit timer compare register 2 (cr2 ): only when using cascade connection timer output to20, to21 control registers note timer clock selection regist ers 20, 21 (tcl20, tcl21) timer clock selection register 2 (tcl2) : only when using cascade connection 8-bit timer mode control registers 20, 21 (tmc20, tmc21) 16-bit timer mode control register 2 (t mc2): only when using cascade connection note when using the functions of the ti2n and to2n pins, see table 4-15 settings when port pins are used for alternate functions .
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 246 (1) 8-bit timer counters 20, 21 (tm20, tm21) the tm2n register is an 8-bit read-only re gister that counts the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. the tm20 and tm21 registers can be used as 16-bit timers when they are connected in cascade. when these timers are used as 16-bit timers, their values can be read by using a 16-bit memory manipulation instruction. tm2n (n = 0, 1) after reset: 00h r address: tm20 fffff640h, tm21 fffff641h 76 54 32 1 0 in the following cases, t he count value becomes 00h. ? reset ? when the tmc2n.tm2cen bit is cleared (0) ? tm2n register and cr2n register match in the mode in which clear & start occurs on a match between the tm2n register and cr2n register caution when connected in cascade, these registers become 0000h even when the tm2ce0 bit in the lowest timer (tm20) is cleared. remark n = 0, 1
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 247 (2) 8-bit timer compare registers 20, 21 (cr20, cr21) the cr2n register can be read and written by an 8-bit memory manipulation instruction. in a mode other than the pwm mode, the value set to the cr2n register is always compared to the count value of the tm2n register, and if the two values match, an interrupt request signal (inttm2n) is generated. in the pwm mode, tm2n register overflow causes the to 2n pin output to change to the active level, and when the values of the tm2n register and the cr2n register match, the to2n pi n output changes to the inactive level. the value of the cr2n register can be set in the range of 00h to ffh. when the tm20 and tm21 registers are connected in ca scade as 16-bit timers, the cr20 register and cr21 register function as 16-bit timer compare register 2 (cr2 ). the count value and register value are compared in 16-bit lengths, and if they match, an inte rrupt request (inttm20) is generated. reset sets these registers to 00h. cr2n (n = 0, 1) after reset: 00h r/w address: cr20 fffff642h, cr21 fffff643h 76 54 32 1 0 cautions 1. in the mode in which clear & start occurs upon a match of the tm2n register and cr2n register (tmc2n.tmc2n6 bit = 0) , do not write a different valu e to the cr2n register during the count operation. 2. in the pwm mode, set the cr2n register re write interval to three or more count clocks (clock selected with the tcl2n register). 3. before changing the value of the cr2n re gister when using a cascade connection, be sure to stop the timer operation. remark n = 0, 1
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 248 9.3 registers the following two registers are used to co ntrol 8-bit timer/event counter 2n. ? timer clock selection register 2n (tcl2n) ? 8-bit timer mode control register 2n (tmc2n) remark to use the functions of the ti2n and to2n pins, see table 4-15 settings when port pins are used for alternate functions . (1) timer clock selection registers 20, 21 (tcl20, tcl21) tcl20 and tcl21 set the count clock of 8-bit timer/event counter 2n and the valid edge of the ti2n pin input. these registers are set by an 8-bit memory manipulation instruction. reset sets these registers to 00h. falling edge of ti2n rising edge of ti2n f xx /4 f xx /8 f xx /16 f xx /32 f xx /128 f xx /512 count clock selection tcl2n2 0 0 0 0 1 1 1 1 tcl2n1 0 0 1 1 0 0 1 1 tcl2n0 0 1 0 1 0 1 0 1 20 mhz 10 mhz ? ? 200 ns 400 ns 800 ns 1.60 s 6.40 s 25.6 s ? ? 400 ns 800 ns 1.60 s 3.20 s 12.8 s 51.2 s clock f xx 0 tcl2n (n = 0, 1) 0 0 0 0 tcl2n2 tcl2n1 tcl2n0 after reset: 00h r/w address: tcl20 fffff644h, tcl21 fffff645h 76 54 32 1 0 cautions 1. before overwriting the tcl2n regist er with different data, stop the timer operation. 2. because the ti2n pin functi ons alternately as p03/intp2 and p14/to21, select the timer input function by setting the pmc0, pfc0, pm c1, and pfc1 registers before starting the timer operation when using the ti2n pin function . if the ti2n pin is manipulated after the timer operation, the edge detection operation is not performed correctly. remark when tcl2n is connected in cascade, the tcl1 register settings are invalid.
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 249 (2) 8-bit timer mode control registers 20, 21 (tmc20, tmc21) the tmc2n register performs the following six settings. ? controls counting by 8-bit time r counters 20, 21 (tm20, tm21) ? selects the operation mode of the tm2n register ? selects the individual mode or cascade connection mode ? sets the status of t he timer output flip-flop ? controls the timer output flip-flop or selects t he active level in the pwm (free-running) mode ? controls timer output the tmc2n register is set by an 8-bit or 1-bit memory manipulation instruction. reset sets these registers to 00h. remark n = 0, 1
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 250 tm2cen counting is disabled after the counter is cleared to 0 (counter disabled) start count operation tm2cen 0 1 control of count operation of 8-bit timer/event counter 2n tmc2n (n = 0, 1) tmc2n6 0 tmc214 note lvs2n lvr2n tmc2n1 toe2n mode in which clear & start occurs on match between tm2n register and cr2n register pwm (free-running) mode tmc2n6 0 1 selection of operation mode of 8-bit timer/event counter 2n individual mode cascade connection mode (connected with tm20) tmc214 0 1 selection of individual mode or cascade connection mode unchanged reset timer output f/f to 0 set timer output f/f to 1 setting prohibited lvs2n 0 0 1 1 setting of status of timer output f/f lvr2n 0 1 0 1 after reset: 00h r/w address: tmc20 fffff646h, tmc21 fffff647h disable inversion operation enable inversion operation high active low active tmc2n1 0 1 other than pwm (free-running) mode (tmc2n6 = 0) controls timer f/f pwm (free-running) mode (tmc2n6 = 1) selects active level disable output (to2n pin is low level) enable output toe2n 0 1 timer output control <7> 6 5 4 <3> <2> 1 <0> note bit 4 of the tmc20 register is fixed to 0. cautions 1. the lvs2n and lvr2n bit settings are valid in other than the pwm mode. 2. do not rewrite the following bits at the same time. ? tmc2n1 bit and toe2n bit ? tmc2n6 bit and toe2n bit ? tmc2n1 bit and tmc2n6 bit ? tmc2n6 bit and lvs2 n bit or lvr2n bit ? toe2n bit and lvs2n bit or lvr2n bit remarks 1. in the pwm mode, the pwm output is set to the inactive level by setting tm2cen bit = 0. 2. when the lvs2n and lvr2n bits are read, 0 is read. 3. the values of the tmc2n6, lvs 2n, lvr2n, tmc2n1, and toe2n bits are reflected to the to2n output regardless of the tm2cen bit value.
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 251 9.4 operation 9.4.1 operation as interval timer (8 bits) 8-bit timer/event counter 2n operates as an interval timer th at repeatedly generates interr upts at the interval of the count value preset in the cr2n register. if the count value in the tm2n register matches the value set in the cr2n register, the value of the tm2n register is cleared to 00h and counting is continued, and at the same time, an interrupt request signal (inttm2n) is generated. setting method <1> set each register. ? tcl2n register: selects the count clock (t). ? cr2n register: compare value (n) ? tmc2n register: stops count operation and selects the mode in which clear & start occurs on a match between the tm2n register and cr2n register (tmc2n register = 0000xx11b, x: don?t care). <2> when the tmc2n.tm2cen bit is set to 1, the count operation starts. <3> when the values of the tm2n regi ster and cr2n register match, the inttm2n signal is generated (tm2n register is cleared to 00h). <4> then, the inttm2n signal is repeatedly generated at the same interval. to stop counting, clear the tm2cen bit to 0. interval time = (n + 1) t: n = 00h to ffh caution during interval timer operation, do not rewrite the value of the cr2n register. figure 9-2. timing of interval timer operation (1/2) basic operation t interval time interval time 00h n 01h 01h 00h n n n n n n 01h 00h clear interrupt acknowledgment interrupt acknowledgment clear count clock tm2n count value cr2n to2n tm2cen inttm2n count start remark n = 0, 1
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 252 figure 9-2. timing of interval timer operation (2/2) when cr2n register = 00h t interval time 00h 00h 00h 00h 00h count clock tm2n count value cr2n tm2cen inttm2n to2n remark n = 0, 1 when cr2n register = ffh t 01h 00h feh ffh 00h feh ffh 00h ffh ffh ffh count clock tm2n count value cr2n tm2cen inttm2n to2n interval time interrupt acknowledgment interrupt acknowledgment remark n = 0, 1
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 253 9.4.2 operation as external event counter (8 bits) the external event counter c ounts the number of clock pulses input to the ti2n pin from an external source by using the tm2n register. each time the valid edge specified by the tcl2n register is input to the ti2n pin, the tm 2n register is incremented. either the rising edge or the falling e dge can be specified as the valid edge. when the count value of the tm2n register matches the valu e of the cr2n register, the tm2n register is cleared to 00h and an interrupt request signal (inttm2n) is generated. setting method <1> set each register. ? tcl2n register: selects the ti2n input edge. falling edge of ti2n pin tcl2n register = 00h rising edge of ti2n pin tcl2n register = 01h ? cr2n register: compare value (n) ? tmc2n register: stops count operation, selects t he mode in which clear & start occurs on a match between the tm2n register and cr2n register, disables timer output f/f inversion operation, and disables timer output. (tmc2n register = 0000xx00b, x: don?t care) ? for the alternate-function pin settings, see table 4-15 settings when port pins are used for alternate functions . <2> when the tmc2n.tm2cen bit is set to 1, the counter counts the number of pulses input from the ti2n pin. <3> when the values of the tm2n regi ster and cr2n register match, the inttm2n signal is generated (tm2n register is cleared to 00h). <4> then, the inttm2n signal is generated each time the values of the tm2n register and cr2n register match. inttm2n is generated when the valid edge of ti2n is input n + 1 times: n = 00h to ffh caution during external event counter operation, do not rewrite the value of the cr2n register. remark n = 0, 1 figure 9-3. timing of external event coun ter operation (with ri sing edge specified) 00h 01h 02h 03h 04h 05h n ? 1 n n 00h 01h 02h 03h ti2n cr2n inttm2n tm2cen tm2n count value count start remark n = 0, 1
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 254 9.4.3 square-wave output oper ation (8-bit resolution) a square wave with any frequency can be output at an interval determined by the value preset in the cr2n register. by setting the tmc2n.toe2n bit to 1, the output status of the to2n pin is inverted at an interval determined by the count value preset in the cr2n register. in this way, a sq uare wave of any frequency can be output (duty = 50%) (n = 0, 1). setting method <1> set each register. ? tcl2n register: selects the count clock (t). ? cr2n register: compare value (n) ? tmc2n register: stops count operation, selects t he mode in which clear & start occurs on a match between the tm2n register and cr2n register, makes the timer output initial setting, enables timer output f/f inversion operation, and enables timer output. (tmc2n register = 00001011b or 00000111b) ? for the alternate-function pin settings, see table 4-15 settings when port pins are used for alternate functions . <2> when the tmc2n.tm2cen bit is set to 1, counting starts. <3> when the values of the tm2n register and cr2n regi ster match, the timer output f/f is inverted. moreover, the inttm2n signal is generated and the tm2n register is cleared to 00h. <4> then, the timer f/f is inverted during the same inte rval and a square wave is output from the to2n pin. frequency = 1/2t (n + 1): n = 00h to ffh caution do not rewrite the value of the cr2 n register during square-wave output.
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 255 figure 9-4. timing of square-wave output operation 00h 01h 02h n ? 1 n 01h 02h n n 00h count clock cr2n to2n note tm2n count value inttm2n tm2cen count start 00h n ? 1 t note the initial value of the to2n output can be set using the tmc2n.lvs2n and tmc2n.lvr2n bits. remark n = 0, 1
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 256 9.4.4 8-bit pwm output operation by setting the tmc2n.tmc2n6 bit to 1, 8-bit timer/event counter 2n performs pwm output. pulses with the duty factor determined by the value set in the cr2n register are output from the to2n pin. set the width of the active level of the pwm pulse in the cr2n register. the active level can be selected using the tmc2n.tmc2n1 bit. the count clock can be select ed using the tcl2n register. pwm output can be enabled/disabled by the tmc2n.toe2n bit. caution the cr2n register rewrite in terval must be three or more operation clocks (set by the tcl2n register). usage method <1> set each register. ? tcl2n register: selects the count clock (t). ? cr2n register: compare value (n) ? tmc2n register: stops count operation, select s pwm mode, leaves timer output f/f unchanged, sets active level, and enables timer output. (tmc2n register = 01000001b or 01000011b) ? for the alternate-function pin settings, see table 4-15 settings when port pins are used for alternate functions . <2> when the tmc2n.tm2cen bit is set to 1, counting starts. pwm output operation <1> when counting starts, pwm output (output from th e to2n pin) outputs the inactive level until an overflow occurs. <2> when an overflow occurs, the active level set by setting method <1> is output. the active level is output until the value of the cr2n register and the count value of the tm2n register match. <3> when the value of the cr2n register and the co unt value match, the inactive level is output and continues to be output until an overflow occurs again. <4> then, steps <2> and <3> are repe ated until counting is stopped. <5> when counting is stopped by clearing the tm2cen bit to 0, pwm output becomes inactive. cycle = 2 8 t, active level width = nt, duty = n/2 8 : n = 00h to ffh remarks 1. n = 0, 1 2. for the detailed timing, see figure 9-5 timing of pwm output operation and figure 9-6 timing of operation based on cr2n register transitions .
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 257 (a) basic operation of pwm output figure 9-5. timing of pwm output operation basic operation (active level = h) 00h n + 1 n n 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h active level inactive level active level count clock tm2n count value cr2n tm2cen inttm2n to2n t when cr2n register = 00h 00h n + 1 n + 2 n 00h 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h inactive level inactive level count clock tm2n count value cr2n tm2cen inttm2n to2n t when cr2n register = ffh 00h n + 1 n + 2 n ffh 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h inactive level inactive level inactive level active level active level count clock tm2n count value cr2n tm2cen inttm2n to2n t remark n = 0, 1
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 258 (b) operation based on cr2n register transitions figure 9-6. timing of operation b ased on cr2n register transitions when the value of the cr2n register changes from n to m before the rising edge of the ffh clock the value is transferred to the cr2n register at the overflow that occurs immediately after. n n + 1 n + 2 m n <1> cr2n transition (n m) m m + 1 m + 2 m m + 1 m + 2 ffh 02h 00h 01h ffh 02h 00h 01h count clock tm2n count value cr2n tm2cen h inttm2n to2n <2> t when the value of the cr2n register changes from n to m after the rising edge of the ffh clock the value is transferred to the cr2n register at the second overflow. n n + 1 n + 2 n nn <1> cr2n transition (n m) m n + 1 n + 2 m m + 1 m + 2 ffh 03h 02h 00h 01h ffh 02h 00h 01h count clock tm2n count value cr2n tm2cen h inttm2n to2n <2> t caution in the case of read from the cr2n register between <1> and <2>, the value that is actually used differs (read value: m; actual value of cr2n register: n). remark n = 0, 1
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 259 9.4.5 operation as inte rval timer (16 bits) the 16-bit resolution timer/event counter mode is selected by setting the tmc21.tmc214 bit to 1. 8-bit timer/event counter 2n operates as an interval time r by repeatedly generating interrupts using the count value preset in the cr2 register as the interval. setting method <1> set each register. ? tcl20 register: selects the count clock (t) (the tcl21 register does not need to be set in cascade connection) ? cr20 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr21 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc20, tmc21 registers: selects the mode in wh ich clear & start occurs on a match between tm2 register and cr2 register (x: don?t care) tmc20 register = 0000xx11b tmc21 register = 0001xx00b <2> set the tmc21.tm2ce1 bit to 1. then set the tm c20.tm2ce0 bit to 1 to start the count operation. <3> when the values of the tm2 r egister and cr2 register connected in cascade match, the inttm20 signal is generated (the tm2 register is cleared to 0000h). <4> the inttm20 signal is then generated repeatedly at the same interval. interval time = (n + 1) t: n = 0000h to ffffh cautions 1. to write using 8- bit access during cascade connection, set the tm2ce1 bit to 1 at operation start and then set the tm2ce0 bit to 1. when operation is stopped, clear the tm2ce0 bit to 0 and then clear the tm2ce1 bit to 0. 2. during cascade connection, use ti20 input, to20 output, and inttm20 and do not use and mask ti21 input, to21 output, a nd inttm21 (for details, see chapter 16 interrupt/exception processing function ). clear bits lvs21, lvr21, tmc211, and toe21 to 0. 3. do not change the value of the cr2 register during timer operation.
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 260 figure 9-7 shows a timing example of the cascade connection mode with 16-bit resolution. figure 9-7. cascade connection mode with 16-bit resolution 00h n + 1 01h 00h ffh 00h 01h ffh 00h ffh m ? 1 01h 00h 00h na 01h 00h 02h m 00h 00h b n n m interval time operation enabled, count start interrupt occurrence, counter cleared operation stopped count clock tm20 count value tm21 count value tm2ce1 inttm20 to20 cr21 tm2ce0 cr20 t
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 261 9.4.6 operation as external event counter (16 bits) the 16-bit resolution timer/event counter mode is selected by setting the tmc21.tmc214 bit to 1. the external event counter counts the number of clock puls es input to the ti20 pin from an external source using the tm2 register. setting method <1> set each register. ? tcl20 register: selects the ti20 input edge. (the tcl21 register does not have to be set during cascade connection.) falling edge of ti20 tcl20 register = 00h rising edge of ti20 tcl20 register = 01h ? cr20 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr21 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc20, tmc21 registers: stops co unt operation, selects the clear & start mode entered on a match between the tm2 register and cr2 regi ster, disables timer output f/f inversion, and disables timer output. (x: don?t care) tmc20 register = 0000xx00b tmc21 register = 0001xx00b ? for the alternate-function pin settings, see table 4-15 settings when port pins are used for alternate functions . <2> set the tmc21.tm2ce1 bit to 1. then set the tmc 20.tm2ce0 bit to 1 and count the number of pulses input from ti20. <3> when the values of the tm2 r egister and cr2 register connected in cascade match, the inttm20 signal is generated (the tm2 register is cleared to 0000h). <4> inttm20 is then generated each time the values of the tm2 register and cr2 register match. inttm20 is generated when the valid edge of ti 20 is input n + 1 times: n = 0000h to ffffh cautions 1. during external event counter ope ration, do not rewrite the value of the cr2n register. 2. to write using 8-bit access during cascade connection, set the tm2ce1 bit to 1 and then set the tm2ce0 bit to 1. when opera tion is stopped, clear the tm2ce0 bit to 0 and then clear the tm2ce1 bit to 0. 3. during cascade connection, use ti20 in put and inttm20 and do not use and mask ti21 input, to21 output, and inttm21 (for details, see chapter 16 interrupt/exception processing function ). clear bits lvs21, lvr21, tmc211, and toe21 to 0. 4. do not change the value of the cr2 regi ster during external event counter operation.
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 262 9.4.7 square-wave output oper ation (16-bit resolution) the 16-bit resolution timer/event counter mode is selected by setting the tmc21.tmc214 bit to 1. 8-bit timer/event counter 2n outputs a square wave of any frequency using the interval preset in the cr2 register. setting method <1> set each register. ? tcl20 register: selects the count clock (t) (the tcl21 register does not have to be set in cascade connection) ? cr20 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr21 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc20, tmc21 registers: stops c ount operation, selects the mode in which clear & start occurs on a match between the tm2 register and cr2 register. lvs20 lvr20 timer output f/f status settings 1 0 high-level output 0 1 low-level output enables timer output f/f inversion, and enables timer output. tmc20 register = 00001011b or 00000111b tmc21 register = 00010000b ? for the alternate-function pin settings, see table 4-15 settings when port pins are used for alternate functions . <2> set the tmc21.tm2ce1 bit to 1. then set the tm c20.tm2ce0 bit to 1 to start the count operation. <3> when the values of the tm2 regi ster and the cr2 register connected in cascade match, the to20 timer output f/f is inverted. moreover, the inttm20 signal is generated and the tm2 register is cleared to 0000h. <4> then, the timer f/f is inverted during the same inte rval and a square wave is out put from the to20 pin. frequency = 1/2t (n + 1): n = 0000h to ffffh caution do not write a differen t value to the cr2 register.
chapter 9 8-bit timer/event counters 20 and 21 user?s manual u16237ej3v0ud 263 9.5 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because the tm2n register is started asynchronously to the count pulse. figure 9-8. start timing of timer 2n 00h timer start 01h 02h 03h 04h count pulse tm2n count value remark n = 0, 1
user?s manual u16237ej3v0ud 264 chapter 10 real-time counter function 10.1 functions the real-time counter ha s the following functions. ? week, day, hour, minute, and second counters that can count up to 4,095 weeks ? week, day, hour, minute, and second counters can be read while they are operating/stopped ? generates overflow interrupt request signal (introv) from week counter. ? generates interval interrupt request signal (intrtc) at in tervals of 0.015625, 0.03125, 0.0625, 0.125, 0.25, 0.5, or 1 second, 1 minute, 1 hour, or 1 day. 10.2 configuration the block diagram of the real-time counter is shown below. figure 10-1. block diagram of real-time counter selector count enable/ disable circuit sub-count register (subc) (15 bits) second count register (sec) (6 bits) internal bus second count setting register (secb) minute count setting register (minb) hour count setting register (hourb) day count setting register (dayb) week count setting register (weekb) minute count register (min) (6 bits) hour count register (hour) (5 bits) day count register (day) (3 bits) week count register (week) (12 bits) introv intrtc 1 second 6 0.015625/0.03125/0.0625/0.125/0.25/0.5 second 1 minute 1 hour 1 day count clock = 32.768 khz f xt remark f xt : subclock frequency
chapter 10 real-time counter function user?s manual u16237ej3v0ud 265 table 10-1. configuration of real-time counter item configuration registers rtc control register 0 (rtcc0) rtc control register 1 (rtcc1) sub-count register (subc) second count register (sec) second count setting register (secb) minute count register (min) minute count setting register (minb) hour count register (hour) hour count setting register (hourb) day count register (day) day count setting register (dayb) week count register (week) week count setting register (weekb) 10.3 registers the registers listed in the table bel ow control the real-time counter. (1) rtc control register 0 (rtcc0) rtcc0 is an 8-bit register that controls the operation of the real-time counter. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 80h. rtcc0 stops rtc clock operation and resets sub-count value. enables rtc clock operation. rtcae 0 1 enables/disables rtc operation after reset: 80h r/w address: fffff680h rtcae 0 0 0 0 0 0 0 0 1 2 3 4 5 6 <7>
chapter 10 real-time counter function user?s manual u16237ej3v0ud 266 (2) rtc control register 1 (rtcc1) rtcc1 is an 8-bit register that controls the operation of the real-time counter. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 8xh. rtcc1 disables rtc count operation. enables rtc count operation. rtce 0 1 enables/disables rtc count-up operation count operation is stopped count-up operation is in progress. rtcf 0 1 rtc operation flag does not generate interrupt request signal. generates interrupt request signal every 0.015625 second. generates interrupt request signal every 0.03125 second. generates interrupt request signal every 0.0625 second. generates interrupt request signal every 0.125 second. generates interrupt request signal every 0.25 second. generates interrupt request signal every 0.5 second. generates interrupt request signal every 1 second. generates interrupt request signal every 1 minute . generates interrupt request signal every 1 hour . generates interrupt request signal every 1 day . setting prohibited ints3 0 0 0 0 0 0 0 0 1 1 1 specifies interrupt request signal generation timing other than above ints2 0 0 0 0 1 1 1 1 0 0 0 ints1 0 0 1 1 0 0 1 1 0 0 1 ints0 0 1 0 1 0 1 0 1 0 1 0 after reset: 8xh note 1 r/w address: fffff681h rtce ints3 ints2 ints1 ints0 0 0 rtcf note 2 <0> 1 2 3 4 5 6 <7> notes 1. 80h or 81h, depending on the value of the rtcf bit. 2. the rtcf bit is a read-only bit.
chapter 10 real-time counter function user?s manual u16237ej3v0ud 267 (3) sub-count register (subc) subc is a 15-bit register that counts the reference time of the real-time counter. it counts 1 second using the 32.768 khz clock. this register is read-only, in 16-bit or 8-bit units. this register is not initialized after reset or when rtcc1.rtce bit = 0. subc after reset: undefined r address: fffff682h 0 subc14 to subc0 0 15 14 (4) second count register (sec) sec is an 8-bit register that uses a value of 0 to 59 (decimal) to indicate the count value in seconds. this register is read-only, in 8-bit units. this register is not initialized after reset or when rtcc1.rtce bit = 0. sec after reset: undefined r address: fffff684h 0 0 sec5 sec4 sec3 sec2 sec1 sec0 0 1 2 3 4 5 6 7 (5) second count setting register (secb) secb is an 8-bit register for setting the second count. this register is write-only, in 8-bit units. set a count value in a range of 0 to 59 (decimal) to this register. do not set a count value of 60 (decimal) or greater. reset sets this register to 00h. secb after reset: 00h w address: fffff68ah 0 0 sec5 sec4 sec3 sec2 sec1 sec0 0 1 2 3 4 5 6 7
chapter 10 real-time counter function user?s manual u16237ej3v0ud 268 (6) minute count register (min) min is an 8-bit register that uses a value of 0 to 59 (decimal) to indicate the count value in minutes. this register is read-only, in 8-bit units. this register is not initialized after reset or when rtcc1.rtce bit = 0. min after reset: undefined r address: fffff685h 0 0 min5 min4 min3 min2 min1 min0 0 1 2 3 4 5 6 7 (7) minute count setting register (minb) minb is an 8-bit register for setting the minute count. th is register is write-only, in 8-bit units. set a count value in a range of 0 to 59 (decimal) to this register. do not set a count value of 60 (decimal) or greater. reset sets this register to 00h. minb after reset: 00h w address: fffff68bh 0 0 min5 min4 min3 min2 min1 min0 0 1 2 3 4 5 6 7 (8) hour count register (hour) hour is an 8-bit register that uses a value of 0 to 23 (decimal) to indicate the count value in hours. this register is read-only, in 8-bit units. this register is not initialized after reset or when rtcc1.rtce bit = 0. hour after reset: undefined r address: fffff686h 0 0 0 hour4 hour3 hour2 hour1 hour0 0 1 2 3 4 5 6 7
chapter 10 real-time counter function user?s manual u16237ej3v0ud 269 (9) hour count setting register (hourb) hourb is an 8-bit register for setting the hour count. this register is write-only, in 8-bit units. set a count value in a range of 0 to 23 (decimal) to this register. do not set a count value of 24 (decimal) or greater. reset sets this register to 00h. hourb after reset: 00h w address: fffff68ch 0 0 0 hour4 hour3 hour2 hour1 hour0 0 1 2 3 4 5 6 7 (10) day count register (day) day is an 8-bit register that uses a val ue of 0 to 6 (decimal) to indicate the count value in days. this register is read-only, in 8-bit units. this register is not initialized after reset or when rtcc1.rtce bit = 0. day after reset: undefined r address: fffff687h 0 0 0 0 0 day2 day1 day0 0 1 2 3 4 5 6 7 (11) day count setting register (dayb) dayb is an 8-bit register for setting the day count. this regi ster is write-only, in 8-bit units. set a count value in a range of 0 to 6 (decimal) to this register. do not set a count value of 7 (decimal) or greater. reset sets this register to 00h. dayb after reset: 00h w address: fffff68dh 0 0 0 0 0 day2 day1 day0 0 1 2 3 4 5 6 7
chapter 10 real-time counter function user?s manual u16237ej3v0ud 270 (12) week count register (week) week is a 16-bit register that uses a value of 0 to 4,095 (decimal) to indicate the count value in weeks. this register is read-only, in 8-bit or 16-bit units. this register is not initialized after reset or when rtcc1.rtce bit = 0. week after reset: undefined r address: fffff688h 0000 week11 to week0 0 15 12 11 (13) week count setting register (weekb) weekb is a 16-bit register for setting the week count. this register is write-only, in 8-bit or 16-bit units. set a count value in a range of 0 to 4,095 (decimal) to this register. reset sets this register to 0000h. weekb after reset: 0000h w address: fffff68dh 0000 week11 to week0 0 15 12 11
chapter 10 real-time counter function user?s manual u16237ej3v0ud 271 10.4 operation 10.4.1 initializing counter and count-up <1> after reset, the values of the rtcc0 and rtcc1 regist ers are initialized. real-time counter clock operation is enabled when the rtcc0.rtcae bit is set to 1, and r eal-time counter count operation is enabled when the rtcc1.rtce of bit is set to 1. <2> the sub-count register (subc) is reset if the real -time count clock operation is stopped when the rtcae bit is 0. <3> the real-time counter clock operation is started when the rtcae bit is set to 1. <4> after 3 internal clocks, the values of all the count setting registers are reflected on the corresponding count registers at all once, and each c ount register starts counting up. <5> each time a count register overflows, the higher count register starts counting up. <6> at the clock after the one at which the overflow condit ions of all the count registers have been satisfied, all the count registers are cleared to ?0?. the introv signal is asserted active for the duration of one cycle of the real-time count clock after t he week register overflows. 10.4.2 rewriting counter <1> after reset, the values of the rtcc0 and rtcc1 regist ers are initialized. real-time counter clock operation is enabled when the rtcc1.rtcae bit is set to 1, and r eal-time counter count operation is enabled when the rtcc1.rtce bit is set to 1. <2> write a value to each count setting register. <3> the value of all the count setting registers are re flected on the corresponding count registers all at once two internal clocks after the rtce bit is set to 1, and th e real-time counter starts counting up 3 internal clocks after that. 10.4.3 controlling interrupt request signal output this section explains how to control interrupt request signals, taking the rtcc1.ints0 to rtcc1.ints3 bits = 0111b (every second) and the rtcc1.ints0 to rtcc1.ints3 bits = 1000b (every minute) as an example. <1> after reset, the values of the rtcc0 and rtcc1 regist ers are initialized. real-time counter clock operation is enabled when the rtcc1.rtcae bit is set to 1, and real-time counter count operation is enabled when rtce is set to 1. the subc register is reset. <2> clear the rtcae bit to 0. <3> the internal clock operation is started when the rtcae bit = 1. <4> after 3 internal clocks, the value of all the count setting registers are reflected on the corresponding count registers at all once, and the real -time counter starts counting up. <5> set the ints0 to ints3 bits to 0111b (1000b). <6> because the ints0 to ints3 bits = 0111b, the intrtc signal is asserted each time 1 second is counted (because the ints0 to ints3 bits = 1000b, the intrtc signal is asserted each time 1 minute is counted). <7> the introv signal is asserted when the overflow c onditions of all the count r egisters have been satisfied.
chapter 10 real-time counter function user?s manual u16237ej3v0ud 272 10.4.4 cautions (1) if the real-time counter is not used, clear rtcc0.rtcae to 0 after the reset signal has been cleared. (2) perform initialization after clearing the rtcae bit to 0 when the reset signal has been cleared for the first time. for initialization, set each count setting register, count clock, and interrupt request signal generation timing using the procedure described in (4) and (5) below, an d clear the rovic.rovif bit and the rtcic.rtcif bit to 0. (3) read each count register us ing the following procedure: <1> read the second, minute, hour, day, and week co unt registers in that order, and then read the second count register again. <2> compare the value of the second count register read first with the val ue of the second count register read last. if the two values do not match, the chances are that the counter counted up while it was being read. if so, repeat steps <1> and <2> again. (4) write data to each count setting register using the following procedure: ? to clear the subc register <1> using the procedure described in (3) above, read the values of all the c ount registers (this may be omitted), and clear the rtcae bit to 0. <2> write a value to one of the count setting registers. write the value read in step <1> to the other count setting registers. <3> set the rtcae bit to 1. the values of the c ount setting registers will be transferred to the count registers, and the real-time counter will st art counting (after 2 or 3 count clocks). ? to not clear the subc register (to hold the value) <1> clear the rtcc1.rtce bit to 0, and check if the rtcc1.rtcf bit is cleared to 0 (count stops). <2> read the values of all the count registers (this may be omitted). <3> write a value to one of the count setting register s. write the value read in <2> to the other count setting registers. <4> set the rtce bit to 1. the values of the count setting registers will be transferred to the count registers, and the real-time counter will st art counting (after 2 or 3 count clocks). (5) to change the interrupt request signal generation timi ng, be sure to set the rtcic.rtcmk bit to 1. after changing the timing, clear the rtcic.rtcif bit to 0. (6) to change the count clock, be sure to clear the rtcae bit to 0.
user?s manual u16237ej3v0ud 273 chapter 11 watchdog timer functions 11.1 functions the watchdog timer has the following operation modes. ? watchdog timer ? interval timer the following functions are realized fr om the above-listed operation modes. ? generation of system reset signal (wdt res) upon overflow of watchdog timer ? generation of maskable interrupt request signal (intwdtm) upon overflow of interval timer remark select whether to use the watchdog timer in the wa tchdog timer mode or the interval timer mode using the wdtm register.
chapter 11 watchdog timer functions user?s manual u16237ej3v0ud 274 11.2 configuration the watchdog timer consists of the following hardware. figure 11-1. block diagram of watchdog timer 13-bit divider run wdcs0 to wdcs2 wdtm3, wdtm4 clear clear 8-bit counter output control f xw f xw /2 13 f xw /2 12 f xw /2 11 f xw /2 10 f xw /2 9 f xw /2 8 f xw /2 7 f xw /2 6 f xw /2 5 selector ovf intwdtm wdtres remark intwdtm: request signal for maskable interrupt through wdt overflow wdtres: reset signal through wdt overflow f xw = f xx /16: watchdog timer clock frequency table 11-1. configuration of watchdog timer item configuration control register watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm)
chapter 11 watchdog timer functions user?s manual u16237ej3v0ud 275 11.3 registers the registers that control the watchdog timer are as follows. ? watchdog timer clock select register (wdcs) ? watchdog timer mode register (wdtm) (1) watchdog timer clock select register (wdcs) wdcs is a register that sets the overflow time of the watchdog timer and the interval timer. this register is set by an 8-bit memory manipulation instruction. reset sets this register to 00h. 0 wdcs 0 0 0 0 wdcs2 wdcs1 wdcs0 wdcs2 0 0 0 0 1 1 1 1 overflow time of watchdog timer/interval timer wdcs1 0 0 1 1 0 0 1 1 wdcs0 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff6c1h 2 17 /f xx 2 18 /f xx 2 19 /f xx 2 20 /f xx 2 21 /f xx 2 22 /f xx 2 23 /f xx 2 25 /f xx 20 mhz 10 mhz 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms 838.9 ms 3.355 s 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms 1.678 s f xx remark f xw = f xx /16: watchdog timer clock frequency
chapter 11 watchdog timer functions user?s manual u16237ej3v0ud 276 (2) watchdog timer mode register (wdtm) wdtm is a register that sets the watchdog timer oper ation mode and enables/disables count operations. this register is a special register that c an be written only in a special sequence (see 3.4.7 special registers ). this register is set by an 8-bit or 1-bit memory manipulation instruction. reset sets this register to 00h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the wdtm register using an access method that causes a wait. for details, see 3.4.8 (2). run stops counting clears counter and starts counting run 0 1 selection of operation mode of watchdog timer note 1 wdtm 0 0 wdtm4 wdtm3 0 0 0 after reset: 00h r/w address: fffff6c2h interval timer mode (upon overflow, maskable interrupt intwdtm is generated.) wdtm4 0 0 1 1 wdtm3 0 1 0 1 selection of operation mode of watchdog timer note 2 < > setting prohibited watchdog timer mode (upon overflow, reset operation wdtres is started.) notes 1. once the run bit is set (to 1), it cannot be cleared (to 0) by software. therefore, when counting is started, it cannot be stopped except through reset input. 2. once the wdtm3 and wdtm4 bits are set (to 1), they cannot be cleared (to 0) by software and can be cleared only through reset input. caution it takes up to 2 s (at f xx = 20 mhz) to write the wdtm register because of synchronization control with the wdt operation clock.
chapter 11 watchdog timer functions user?s manual u16237ej3v0ud 277 11.4 operation 11.4.1 operation as watchdog timer watchdog timer operation to detect a program loop is selected by setting the wdtm.wdtm4 and wdtm.wdtm3 bits to 11. the count clock (program loop detection time interv al) of the watchdog timer can be selected with the wdcs.wdcs0 to wdcs.wdcs2 bits. the count operation is started by setting the wdtm.run bit to 1. when, after the count operation is started, the run bit is again se t to 1 within the set program loop detection time interval, the watchdog timer is cleared and t he count operation starts again. if the program loop detection time is exceeded without th e run bit being set to 1, a reset signal (wdtres) is generated. the count operation of the watchdog ti mer stops in the software stop mode and idle mode. set the run bit to 1 before the software stop mode or idle mode is en tered in order to clear the watchdog timer. because the watchdog timer operates in the halt mode, make sure that an overflow will not occur during halt. cautions 1. do not change the mode to the wa tchdog timer mode after clearing the wdtm4 bit to 0 (selecting the interval timer mode ) and setting the run bit to 1. 2. when the subclock is selec ted for the cpu clock, the count operation of the watchdog timer stops (the value of the watchdog timer is maintained). table 11-2. program loop detection time of watchdog timer program loop detection time clock f xx = 20 mhz f xx = 10 mhz 2 17 /f xx 6.554 ms 13.11 ms 2 18 /f xx 13.11 ms 26.21 ms 2 19 /f xx 26.21 ms 52.43 ms 2 20 /f xx 52.43 ms 104.9 ms 2 21 /f xx 104.9 ms 209.7 ms 2 22 /f xx 209.7 ms 419.4 ms 2 23 /f xx 419.4 ms 838.9 ms 2 25 /f xx 1.678 s 3.355 s remark f xw = f xx /16: watchdog timer clock frequency
chapter 11 watchdog timer functions user?s manual u16237ej3v0ud 278 11.4.2 operation as interval timer the watchdog timer can be made to operate as an interval timer that repeatedly generates interrupts using the count value set in advance as the interval , by clearing the wdtm.wdtm4 bit to 0. when the watchdog timer operates as an interval timer, the wdtic.wdtmk flag and priority specification flags (wdtic.wdtpr0 to wdtic.wdtpr2 bits) are valid and maskable interrupt request signals (intwdtm) can be generated. the default prio rity of the intwdtm signal is set to t he highest level among the maskable interrupt request signals. the interval timer continues to operate in the halt m ode, but it stops operating in the software stop mode and the idle mode. cautions 1. once the wdtm4 bit is set to 1 (thereby selecting the watchdog timer mode), the interval timer mode is not entered as long as reset is not input. 2. when the subclock is selec ted for the cpu clock, the count operation of the watchdog timer stops (the value of the watchdog timer is maintained). table 11-3. interval time of interval timer interval time clock f xx = 20 mhz f xx = 10 mhz 2 17 /f xx 6.554 ms 13.11 ms 2 18 /f xx 13.11 ms 26.21 ms 2 19 /f xx 26.21 ms 52.43 ms 2 20 /f xx 52.43 ms 104.9 ms 2 21 /f xx 104.9 ms 209.7 ms 2 22 /f xx 209.7 ms 419.4 ms 2 23 /f xx 419.4 ms 838.9 ms 2 25 /f xx 1.678 s 3.355 s remark f xw = f xx /16: watchdog timer clock frequency
chapter 11 watchdog timer functions user?s manual u16237ej3v0ud 279 11.4.3 monitoring reset by watchdog timer (wdt) when the v850es/pm1 has been reset, whether it has been reset by the watchdog timer (wdtres) can be checked by using the wdres register. (1) wdt reset status register (wdres) wdres is an 8-bit register that indicates the status of wdtres and can be read or written by an 8-bit or 1-bit manipulation instruction. to write the wdres register, a specific sequence us ing the prcmd register as a command register is required. if the register is written in an illegal sequence, writing is invalid and the protect error flag (bit 0 of sys register: prerr) is set to 1, and nothing is written to the register. this register is undefined after reset. wdres wdtres did not occur wdtres occurred setting (1) condition: reset by overflow of watchdog timer (wdt) clearing (0) condition: writing ?0? by instruction or reset pin input. only ?0? can be written to the wresf bit. wresf 0 1 wdtres detection flag after reset: undefined r/w address: fffff82ah 0 0 0 0 0 0 0 wresf <0> 1 2 3 4 5 6 7 caution write ?0? to the wresf bit after confirming (r eading) that the wresf bit is 1 to avoid a conflict with setting the flag. remark the wresf bit can be read or written, but it can onl y be cleared by writing ?0?. ?1? cannot be written to it.
user?s manual u16237ej3v0ud 280 chapter 12 a/d converter 12.1 functions the a/d converter converts an analog input signal into a digital value. its functions are as follows. s/n ratio: 62 db min. (when gain of 16 is selected for channels 1, 3, and 5) 16-bit resolution (conversion result register: 16 bits) 6 channels analog input: 12 (positive, negative input/channel) ? conversion mode pre-amplifier gain selectable: 2 or 16 (channels 1, 3, and 5) operating voltage: av dd = 3.0 to 3.6 v, av ss = 0 v analog input voltage: 0.375 v (channels 0, 2, and 4) 0.1875 v (channels 1, 3, and 5, when pre-amplifier gain of 1 is selected) 23.4 mv (channels 1, 3, and 5, when pre-amplifier gain of 16 is selected) reference voltage generation (1.226 v (typ.) can be output) conversion rate selectable (4.340 khz or 2.170 khz)
chapter 12 a/d converter user?s manual u16237ej3v0ud 281 12.2 configuration the a/d converter consists of the following hardware. figure 12-1. block diagram of a/d converter ? + ? + ? + ? + ? + ? + av dd av ss av refin ani00 ani01 ani20 ani21 ani40 ani41 ani10 ani11 ani30 ani31 ani50 ani51 multiplex ? multiplex ? intad (interrupt request signal) f xx (main clock) internal reset signal internal bus register & selector high- pass filter digital filter (low- pass filter) v ref buffer av refout band-gap reference circuit digital block analog block table 12-1. configuration of a/d converter item configuration analog input 6 channels and 12 inputs (anin0 and anin1 pins (n = 0 to 5)) 2 inputs/channel registers a/d converter mode register (adm) high-pass filter control register 0 (hpfc0) a/d conversion result register n (adcrn) (n = 0 to 5) a/d clock delay setting register (adly) internal units pre-amplifier block ? converter reference voltage generator digital filter (df) high-pass filter (hpf)
chapter 12 a/d converter user?s manual u16237ej3v0ud 282 (1) pre-amplifier this unit shifts the signal input to the anin0 and anin1 pins with av ss as the reference voltage into the internal reference voltage, and then amplifies the input signal. it supplies its output signal to the ? circuit (n = 0 to 5). (2) multiplex ? circuit two 3-multiplex ? circuits are provided so that a total of 6 channels of analog inputs can be converted into digital signals. these two ? circuits operate synchronously, and one ? circuit executes analog input conversion of three channels by time division. the input signal is amplified by the pre-amplifier and ? circuit, and the gain of channels 0, 2, and 4 is fixed to 1, and that of channels 1, 3, and 5 can be selected from 2 and 16. a high-speed mode (4.340 khz) and a low-speed mode (2.170 khz) are selectable as the conversion rate, and the over-sampling frequency in the respective modes is 555.6 khz and 277.8 khz (at f x = 20 mhz). (3) reference voltage generator an internal reference voltage source (band-gap reference circuit) is provided and a reference voltage is output from the reference voltage output pin (av refout ). to use the internal reference voltage source, connect the av refout pin and reference voltage input pin (av refin ) as shown in figure 12-2. to use an external reference voltage source, input its voltage to the av refin pin and leave av refout open. figure 12-2. example of recomme nded external connection of av refin /av refout pin 43 k ? 0.22 f av refout av refin (4) digital filter (df) this unit eliminates high harmonic noise included in the ? circuit and thins out the data rate to 1/128. (5) high-pass filter this unit eliminates the dc component included in the input signal and the dc offset generated by the analog circuit. whether the high-pass filter is inse rted or not can be selected for each channel. (6) anin0 to anin1 pins (n = 0 to 5) these are analog input pins of the a/ d converter. one channel inputs two signals. the anin0 pin is the negative input, while the anin1 pin is the positive input. (7) av dd pin this is the analog power supply pin of the a/d converter. always keep the voltage on this pin the same as that on the v dd pin even when the a/d converter is not used.
chapter 12 a/d converter user?s manual u16237ej3v0ud 283 (8) av ss pin this is the ground pin of the a/d converter. always k eep the voltage on this pin the same as that on the v ss pin even when the a/d converter is not used. (9) av refin pin this pin inputs a reference voltage to the a/d converter. when the internal reference voltage is to be used, connect this pin to the av refout pin. to use an external reference voltage, input the voltage from the av refin pin. (10) av refout pin this pin outputs an internally generated re ference voltage for the a/d converter. leave this pin open when the av refout pin is not used.
chapter 12 a/d converter user?s manual u16237ej3v0ud 284 12.3 registers the a/d converter is controlled by the following registers. (1) a/d converter mode register (adm) adm is a register that controls the operation of the a/d converter and spec ifies the gain of pre-amplifier and conversion rate. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. adpon power off power on adpon 0 1 specification of power to a/d converter adm adce 0 0 0 pags1 0 fr < > < > < > < > after reset: 00h r/w address: fffff200h stop conversion operation enable conversion operation adce 0 1 specification of operation of a/d converter high speed (4.340 khz) low speed (2.170 khz) fr 0 1 specification of conversion rate 2 16 pags1 0 1 specification of programmable amplifier gain of channels 1, 3, and 5 ? use channels 1, 3, and 5 for current measurement. ? use channels 0, 2, and 4 for voltage measurement (the gain of these channels is fixed to 1). caution be sure to clear bits 1 and 3 to 5 to ?0?.
chapter 12 a/d converter user?s manual u16237ej3v0ud 285 (2) high-pass filter control register 0 (hpfc0) hpfc0 is an 8-bit register that specifies insert ion of a high-pass filter for each channel. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 hpfc0 0 thr5 thr4 thr3 thr2 thr1 thr0 < > < > < > < > < > < > after reset: 00h r/w address: fffff202h insert high-pass filter do not insert high-pass filter thrn 0 1 specification of insertion of high-pass filter for channel n (n = 0 to 5) ? if the high-pass filter is not inserted, the scale of the a/d output is decreased to 1/2 to avoid overload due to the dc element. (3) a/d conversion result regi sters 0 to 5 (adcr0 to adcr5) the adcr0 to adcr5 registers are 16-bit registers that store the conversion result of each channel. these registers are read-only, in 16-bit units. the value of these registers is initialized to 0 000h by system reset and when the adm.adce bit is 0. adcrn (n = 0 to 5) after reset: 0000h r/w address: adcr0 fffff204h, adcr1 fffff206h, adcr2 fffff208h, adcr3 fffff20ah, adcr4 fffff20ch, adcr3 fffff20eh 1514131211109876543210 caution read the adcrn register when the adce bit is 1, because the register is initialized when the adce bit is 0. (4) a/d clock delay setting register (adly) adly is a register that controls t he phase between the a/d operation clock and the digital clock. be sure to clear this register to 00h. this register can be read or written in 8-bit units. reset sets this register to 00h. adly after reset: 00h r/w address: fffff201h
chapter 12 a/d converter user?s manual u16237ej3v0ud 286 12.4 operation the a/d converter starts operating when the adm.adpon bit and adm.adce bit are set to 1. the setup time of the analog block and digital filter block is required after powe r application and start of conversion. perform initialization in accordance with the flowchart below. figure 12-3. initialization flowchart clear reset (reset pin l h) turn on power to a/d (adpon bit 1) enable a/d conversion (adce bit 1) wait for setup time set conversion rate, gain, and insertion of high-pass filter execute processing using a/d conversion result number of times intad signal is generated 1,200 note number of times intad signal is generated > 1,200 start a/d converter (hardware reset) note the setup time (the number of times the intad signal is to be generated) when the adpon bit is set to 1 is subject to change. consult nec electronics before using this function. caution if the a/d converter is tempor arily stopped for initialization (adce bit 0 with adpon bit set to 1) and then restarted, it is necessary to wait for a certain setup time. in this case, the setup time should be equal to 10 a/d conversion end interrupt request signals (intad), which is the delay of the digital filter.
chapter 12 a/d converter user?s manual u16237ej3v0ud 287 when a/d conversion is enabled, conversion of the si gnals on the six channels of analog input pins (anin0 and anin1 pins) is started. two sets of 3-multiplex ? circuits are provided, each of which executes conversion of three channels by time division. each time conversion of all th e six channels is completed, the intad signal is generated to inform the cpu that the conversion result can be read. the cycle in which the intad signal is to be generated (t intad ) differs depending on the conversion rate specified by the fr bit of the adm register. to read the adcrn register by interrupt servicing, the maximum pending time is as shown in figure 12-4. complete reading of the adcrn register within this time. remark n = 0 to 5 figure 12-4. timing of generation of int ad signal and storing in adcrn register (f xx = 20 mhz) d0 (n ? 1) d0 (n) d1 (n ? 1) d1 (n) d4 (n ? 1) d4 (n) d5 (n ? 1) d5 (n) d2 (n ? 1) d2 (n) d3 (n ? 1) d3 (n) t intad t rdlim intad adcr0 adcr1 adcr4 adcr5 adcr2 adcr3 t intad : interrupt genera tion cycle: 230.4 s when fr bit = 0, 460.8 s when fr bit = 1 t rdlim : adcrn register read pending time (max.): t intad ? 5.5 a/d system clock (f xx /12) 227.1 s when fr bit = 0, 454.2 s when fr bit = 1
chapter 12 a/d converter user?s manual u16237ej3v0ud 288 12.5 cautions (1) read the adcrn register by a/d conversion end inte rrupt (intad) servicing. otherwise, an illegal value may be read because of a conflict between storing the conversion value in t he adcrn register and reading the register. the period of the intad processing during which reading the adcrn register is held pending differs depending on the specified conversion speed, and is 227.1 s when the adm.fr bit is 0 and 454.2 s when the fr bit is 1 (at 20 mhz). (2) after turning on power to the a/d converter (adm.adpon bit is set to 1), the internal setup time of the a/d converter is necessary. consequently, the data of the first 1,200 conversions is invalid. (3) the setup time is also necessary when the a/d conv erter has been temporarily stopped once for initialization (by clearing the adm.adce bit with the adpon bit set to 1) and then restarted. wait for the duration of 10 intad signals, which is the delay of the digital filter. (4) the time required for the correct data to be output after the conversion operation has been enabled (by setting the adm.adce bit to 1) differs depending on the analog input status at that time . this is because the stabilization time of the high-pass filter ch anges depending on the analog input status. (5) be sure to set the conversion speed and gain, and t he hpfc0 and adly registers while the a/d converter is stopped (adce bit = 0). (6) because the adcrn register is initialized when the a dce bit is 0, read the adcrn register when the adce bit is 1. (7) clear the adpon bit to 0 before shifting to the software stop mode. if software stop mode is entered with the adpon bit set to 1, a current will flow. cautions 1. count the intad signal 1,200 times after the a/d converter is star ted and then load the converted data when the next intad signal is generated. the setup time is subject to change. consult nec electronics before using the setup time. 2. thoroughly evaluate the stabilization time in the environment in which the a/d converter is used. remark n = 0 to 5
user?s manual u16237ej3v0ud 289 chapter 13 pwm function 13.1 features pwmn: 4 channels active level of pwmn output pulse selectable operation clock: selectable from f xx , f xx /2, f xx /4, f xx /8, f xx /16, and f xx /32 pwmn output resolution: selectable from 8, 9, 10, and 12 bits remark n = 0 to 3 13.2 configuration figure 13-1. block diagram of pwm function pwmen pwmcn f pwm alvn prmn1 prmn0 pwpn2 pwpn1 pwpn0 output control block re-load processing pwm counter n (edge latch) comparator pwm compare register n (level latch) pwm buffer register (pwmbn) (edge latch) selector f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 12 12 12 0 to 11 0 to 7 0 to 8 0 to 9 0 to 11 0 to 7 0 to 8 0 to 9 sq 3 pwmn 2 2 overflow match r note note reset function remark n = 0 to 3
chapter 13 pwm function user?s manual u16237ej3v0ud 290 13.3 registers (1) pwm control register n (pwmcn) pwmcn is a register that cont rols the operation of pwmn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 40h. caution to use pwmn, be sure to set the external pins related to pwmn to the control mode. then set the operation clock by using the pwmcn regi ster, set the pwmbn register, and set the pwmen bit to 1. pwmen pwmcn (n = 0 to 3) alvn < > < > prmn1 prmn0 0 pwpn2 pwpn1 pwpn0 stop pwmn operation enable pwmn operation pwmen 0 1 pwmn operation enable/disable active-low active-high alvn 0 1 specification of active level of pwmn 8 bits 9 bits 10 bits 12 bits prmn1 0 0 1 1 prmn0 0 1 0 1 specification of bit length of counter and comparator f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 setting prohibited pwpn2 0 0 0 0 1 1 pwpn1 0 0 1 1 0 0 other than above pwpn0 0 1 0 1 0 1 specification of operation clock of pwmn after reset: 40h r/w address: pwmc0 fffffb00h, pwmc1 fffffb10h, pwmc2 fffffb20h, pwmc3 fffffb30h note when the pwmen bit is set to 1 from 0, pwm counter n is reset and starts counting from 000h (if the bit length is specified as 12 bits). when the counter overflows for the first time, the pwmn signal is asserted. pwm counter n cannot be reset by writing 1 to the pwmen bit while the pwmen bit is already 1. clear the bit to 0 once, and then write 1 to it. remark n = 0 to 3
chapter 13 pwm function user?s manual u16237ej3v0ud 291 (2) pwm buffer register n (pwmbn) pwmbn is a 12-bit buffer register that sets control data of the active sign al width of the pwmn output. bits 15 to 12 of this register are fixed to 0 by hardware. the contents of the pwmbn register are transferred to pwm compare register n when pwm counter n, which controls pwmn output, overflows. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the pwmbn register using an access method that causes a wait. for details, see 3.4.8 (2). remark n = 0 to 3 pwmbn (n = 0 to 3) after reset: 0000h r/w address: pwmb0 fffffb02h, pwmb1 fffffb12h, pwmb2 fffffb22h, pwmb3 fffffb32h 15 14 13 12 11 00000 pwmbn11 to pwmbn0 caution to execute writing to the pwmbn regi ster during pwmn operat ion, the access time is extended by a control action to synchronize th e operation clock. how much the access time is to be extended differs depending on the specifi ed pwmn operation clock. it is the shortest at 1 s (f xx = 20 mhz) when f xx is selected. the access time is lengthened as the operating clock frequency decreases, and the maximum access time is about 4 s (f xx = 20 mhz) when f xx /32 is selected.
chapter 13 pwm function user?s manual u16237ej3v0ud 292 13.4 operation 13.4.1 basic operation to output the pwmn pulse, set the necessary data to the pwmcn and pwmbn registers, and set the pwmcn.pwmen bit to 1. as a result, pwm counter n is cl eared (to 000h). when the counter overflows for the first time, the active level of the pwmn output is set and the da ta of the pwmbn register is transferred to pwm compare register n. after that, the pwmn output is deasserted when the value of pwm counter n matches that of pwm compare register n. this is repeated and the pwmn signal of the active level specified by the alvn bit of the pwmcn register is output from the pwmn pin. when the pwmcn.pwmen bit is cleared to 0, the pwmn output is immediately disabled, and the pwmn output goes to the inactive level specified by the pwmcn.alvn bit. if the pwmcn.pwpn0 to pwmcn.pwpn2 bits, pwmcn.prm0 or pwmcn.prm1 bit, or pwmcn.alvn bit are changed while the pwmn signal is being output, the cycle wid th and pulse width of the pwmn signal cannot be guaranteed during the period in which the change is made. remark n = 0 to 3 figure 13-2. pwmn operation timing 00 00 01 fd fe fe 00 ff fe 01 02 03 fe fd ff 00 01 pwm counter n count start fe count full count count clock pwm counter n overflow signal pwmbn register pwmen bit pwm compare register n comparator match signal pwmn (output) reload set reset set remark n = 0 to 3
chapter 13 pwm function user?s manual u16237ej3v0ud 293 figure 13-3. operation timing when pwmbn register is set to 00h/ffh fe ff 00 00h 00h 01 02 fe ff 00 01 02 fe ff 00 01 pwmn = 00h count clock pwm counter n overflow signal pwmbn register pwm compare register n comparator match signal not set to active level pwmn (output) fe ff 00 01 02 fe ff ffh ffh 00 01 02 fe ff 00 01 pwmn = ffh count clock pwm counter n overflow signal pwmbn register pwm compare register n comparator match signal pwmn (output) 1 count
chapter 13 pwm function user?s manual u16237ej3v0ud 294 13.4.2 repeat frequency the repeat frequency of pwmn output is shown below (n = 0 to 3). pwmn operation frequency resolution repeat frequency ( ): value at f xx = 20 mhz 8 bits f xx /2 8 (approx. 78.13 khz) 9 bits f xx /2 9 (approx. 39.06 khz) 10 bits f xx /2 10 (approx. 19.53 khz) f xx 12 bits f xx /2 12 (approx. 4.88 khz) 8 bits f xx /2 9 (approx. 39.06 khz) 9 bits f xx /2 10 (approx. 19.53 khz) 10 bits f xx /2 11 (approx. 9.77 khz) f xx /2 12 bits f xx /2 13 (approx. 2.44 khz) 8 bits f xx /2 10 (approx. 19.53 khz) 9 bits f xx /2 11 (approx. 9.77 khz) 10 bits f xx /2 12 (approx. 4.88 khz) f xx /4 12 bits f xx /2 14 (approx. 1.22 khz) 8 bits f xx /2 11 (approx. 9.77 khz) 9 bits f xx /2 12 (approx. 4.88 khz) 10 bits f xx /2 13 (approx. 2.44 khz) f xx /8 12 bits f xx /2 15 (approx. 610 hz) 8 bits f xx /2 12 (approx. 4.88 khz) 9 bits f xx /2 13 (approx. 2.44 khz) 10 bits f xx /2 14 (approx. 1.22 khz) f xx /16 12 bits f xx /2 16 (approx. 305 hz) 8 bits f xx /2 13 (approx. 2.44 khz) 9 bits f xx /2 14 (approx. 1.22 khz) 10 bits f xx /2 15 (approx. 610 hz) f xx /32 12 bits f xx /2 17 (approx. 153 hz)
chapter 13 pwm function user?s manual u16237ej3v0ud 295 13.5 cautions each pwmn pin (n = 0 to 3) functions alternately as the p1 n pin (n = 0 to 3) of port 1. to use the pwmn pin, set the corresponding bit of the pmc1 register to 1. for the pin that also functions alternately as a timer output as well as a port pin (p11, p12, and p13), the pfc1 register is used to specify the alternate function. set the corresponding bit of this register to 1. the setting values of the pmc1 and pfc1 registers when pwmn is output are shown below. if the setting of the corresponding bits of the pmc1 and pf c1 registers is changed while the pwmn pulse is being output, the pwmn pulse output cannot be guaranteed. pin function pmc1 register setting pfc1 register setting p10 pwm0 pmc10 bit = 1 setting unnecessary to00 pmc11 bit = 1 pfc11 bit = 0 p11 pwm1 pmc11 bit = 1 pfc11 bit = 1 to01 pmc12 bit = 1 pfc12 bit = 0 p12 pwm2 pmc12 bit = 1 pfc12 bit = 1 to20 pmc13 bit = 1 pfc13 bit = 0 p13 pwm3 pmc13 bit = 1 pfc13 bit = 1
user?s manual u16237ej3v0ud 296 chapter 14 asynchronous serial interface n (uartn) 14.1 features ? transfer rate: 300 bps to 312.5 kbps (using a dedicated baud rate generator and an internal system clock of 20 mhz) ? full-duplex communications on-chip receive buffer register n (rxbn) on-chip transmit buffer register n (txbn) ? two-pin configuration txdn: transmit data output pin rxdn: receive data input pin ? reception error detection functions ? parity error ? framing error ? overrun error ? interrupt sources: 3 types ? reception error interrupt (intsren): interrupt is generated according to the logical or of the three types of reception errors ? reception completion interrupt (intsrn): interrupt is generated when receive data is transferred from the shift register to receive buffer register n after serial transfer is completed during a reception enabled state ? transmission completion interrupt (intstn): interrupt is generated when the serial transmission of transmit data (8 or 7 bits) from the shift register is completed ? character length: 7 or 8 bits ? parity functions: odd, even, 0, or none ? transmission stop bits: 1 or 2 bits ? on-chip dedicated baud rate generator remark n = 0, 1
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 297 14.2 configuration table 14-1. configuration of uart item configuration registers receive buffer register n (rxbn) transmit buffer register n (txbn) receive shift register transmit shift register asynchronous serial interface mode register n (asimn) asynchronous serial interface status register n (asisn) asynchronous serial interface tran smit status register n (asifn) other reception control parity check addition of transmissi on control parity figure 14-1 shows the configuration of a synchronous serial interface n (uartn). (1) asynchronous serial interfa ce mode register n (asimn) asimn is an 8-bit register that specifies the o peration of the asynchronous serial interface. (2) asynchronous serial interfa ce status register n (asisn) asisn consists of a set of flags that indicate the e rror contents when a reception error occurs. the various reception error flags are set (1) when a reception error occurs and are reset (0) when the asisn register is read. (3) asynchronous serial interface tran smit status register n (asifn) asifn is an 8-bit register that indicates the status when a transmit operation is performed. this register consists of a transmit buffer data flag, wh ich indicates the hold status of the data of the txbn register, and the transmit shift register data flag, which indicates whether transmission is in progress. (4) reception control parity check the receive operation is controlled according to the c ontents set in the asimn register. a check for parity errors is also performed during a receive operation, and if an error is detected, a value corresponding to the error contents is set in the asisn register. (5) receive shift register this is a shift register that converts the serial data that was input to the rxdn pin into parallel data. one byte of data is received, and if a stop bi t is detected, the receive data is transferred to the rxbn register. this register cannot be directly manipulated. (6) receive buffer register n (rxbn) rxbn is an 8-bit buffer register for holding receive data. when 7 characters are received, 0 is stored in the msb. during a reception enabled state, re ceive data is transferred from the re ceive shift register to the rxbn register, synchronized with the end of t he shift-in processing of one frame. also, the reception completion interrupt request (intsr n) is generated by the trans fer of data to the rxbn register.
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 298 (7) transmit shift register this is a shift register that conver ts the parallel data that was transferred from the txbn register into serial data. when one byte of data is transferred fr om the txbn register, the shift regi ster data is output from the txdn pin. the transmission completion interrupt request (intstn) is generated synchronized with the completion of transmission of one frame. this register cannot be directly manipulated. (8) transmit buffer register n (txbn) the txbn register is an 8-bit buffer for transmit data. a tr ansmit operation is started by writing transmit data to the txbn register. (9) addition of transmission control parity a transmit operation is controlled by adding a start bit, parit y bit, or stop bit to the data that is written to the txbn register, according to the contents that were set in the asimn register. figure 14-1. block diagram of asynchronous serial interface n parity framing overrun internal bus asynchronous serial interface mode register n (asimn) receive buffer register n (rxbn) receive shift register reception control parity check transmit buffer register n (txbn) transmit shift register addition of transmission control parity baud rate generator n intsren intsrn intstn txdn rxdn selector note note use the pfc30 bit to switch rxd0 and the pfc43 bit to switch rxd1. remarks 1. for the configuration of the baud rate generator, see figure 14-12 . 2. n = 0, 1
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 299 14.3 registers (1) asynchronous serial interfa ce mode register n (asimn) asimn is an 8-bit register that cont rols the uartn transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. cautions 1. when using uartn, be sure to set th e external pins related to uartn functions to the control mode before setting clock select regi ster n (cksrn) and ba ud rate generator control register n (brgcn), and then set th e uartcaen bit to 1. then set the other bits. 2. set the uartcaen and rxen bits to 1 while a high level is being input to the rxdn pin. if these bits are set to 1 while a low le vel is being input to the rxdn pin, reception will be started. (1/3) <7> uartcaen asimn <6> txen <5> rxen 4 psn1 3 psn0 2 cln 1 sln 0 isrmn after reset: 01h r/w address: asim0 fffffa00h, asim1 fffffa10h uartcaen controls the operating clock 0 stops clock supply to uartn. 1 supplies clock to uartn. ? if uartcaen bit = 0, uartn is asynchronously reset note . ? if uartcaen bit = 0, uartn is reset. to operate uartn, first set the uartcaen bit to 1. ? if the uartcaen bit is changed from 1 to 0, all the registers of uartn are initialized. to set the uartcaen bit to 1 again, be sure to re-set the registers of uartn. ? the output of the txdn pin goes high when transmission is disabled, regardless of the setting of the uartcaen bit. txen enables/disables transmission 0 disables transmission 1 enables transmission ? set the txen bit to 1 after setting the uartcaen bit to 1 at startup. clear the uartcaen bit to 0 after clearing the txen bit to 0 to stop. ? to initialize the transmission unit, clear (0) the txen bit, and after letting 2 clock cycles (base clock) elapse, set (1) the txen bit again. if the txen bit is not set again, initialization may not be successful . (for details of the base clock, see 14.6 (1) (a) base clock (clock) .) note the asisn, asifn, and rxbn registers are reset.
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 300 (2/3) rxen enables/disables reception 0 disables reception note 1 enables reception ? set the rxen bit to 1 after setting the uartcaen bit to 1 at startup. clear the uartcaen bit to 0 after clearing the rxen bit to 0 to stop. ? to initialize the reception unit status, clear (0) the rxen bit, and after letting 2 clock cycles (base clock) elapse, set (1) the rxen bit again. if the rxen bit is not set again, initialization may not be succ essful. (for details of the base clock, see 14.6 (1) (a) base clock (clock) .) psn1 psn0 transmit operation receive operation 0 0 parity bit not output receive with no parity 0 1 output 0 parity receive as 0 parity 1 0 output odd parity judge as odd parity 1 1 output even parity judge as even parity ? to overwrite the psn1 and psn0 bits, first clear (0) the txen and rxen bits. ? if ?0 parity? is selected for reception, no parity judgment is performed. therefore, no parity error interrupt is generated because the asisn.pe bit is not set. note when reception is disabled, the receive shift register does not detect a start bit. no shift-in processing or transfer processing to the rxbn register is performed, and the contents of the rxbn register are retained. when reception is enabled, the receive shift operation starts, synchronized with the detection of the start bit, and when the reception of one frame is completed, the contents of the receive shift register are transferred to the rxbn register. a reception comple tion interrupt (intsrn) is also generated in synchronization with the transfer to the rxbn register.
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 301 (3/3) cln specifies character length of 1 frame of transmit/receive data 0 7 bits 1 8 bits ? to overwrite the cln bit, first clear (0) the txen and rxen bits. sln specifies stop bit length of transmit data 0 1 bit 1 2 bits ? to overwrite the sln bit, first clear (0) the txen bit. ? since reception is always performed with a stop bit length of 1, the sl bit setting does not affect receive operations. isrmn enables/disables generation of reception completion interrupt requests when an error occurs 0 generate a reception error interrupt request (intsren) as an interrupt when an error occurs. in this case, no reception completion interrupt request (intsrn) is generated. 1 generate a reception completion interrupt request (intsrn) as an interrupt when an error occurs. in this case, no reception error interrupt request (intsren) is generated. ? to overwrite the isrmn bit, first clear (0) the rxen bit.
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 302 (2) asynchronous serial interfa ce status register n (asisn) the asisn register, which consists of 3 error flag bits (pen, fen and oven), indicates the error status when uartn reception is complete. the asisn register is cleared to 00h by a read operation. when a reception error occurs, the rxbn register should be read and the error flag should be cl eared after the asisn register is read. this register is read-only, in 8-bit units. reset sets this register to 00h. cautions 1. when the asimn.uartcaen bit or asimn. rxen bit is cleared to 00, or when the asisn register is read, the asisn.pen, asisn.fen, and asisn.oven bits are cleared (0). 2. operation using a bit manipula tion instruction is prohibited. 7 0 asisn 6 0 5 0 4 0 3 0 2 pen 1 fen 0 oven after reset: 00h r address: asis0 fffffa03h, asis1 fffffa13h pen status flag that indicates a parity error 0 when the asimn.uartcaen and asimn.rxen bits are both cleared to 0, or when the asisn register has been read 1 when reception was completed, the transmit data parity did not match the parity bit ? the operation of the pen bit differs according to the settings of the asimn.ps1 and asimn.ps0 bits. fen status flag that indicates a framing error 0 when the asimn.uartcaen and asimn.rxen bits are both cleared to 0, or when the asisn register has been read 1 when reception was completed, no stop bit was detected ? for receive data stop bits, only the first bit is checked regardless of the stop bit length. oven status flag that indicates an overrun error 0 when the asimn.uartcaen and asimn.rxen bits are both 0, or when the asisn register has been read. 1 uartn completed the next receive operation before reading the receive data of the rxbn register. ? when an overrun error occurs, the next receive data value is not written to the rxbn register and the data is discarded.
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 303 (3) asynchronous serial interface tran smit status register n (asifn) the asifn register, which consists of 2 status flag bits, indicates the status during transmission. by writing the next data to the txbn register after data is transferred from the txbn register to the transmit shift register, transmit operations can be performed c ontinuously without suspension even during an interrupt interval. when transmission is performed continuously, da ta should be written after referencing the txbfn bit to prevent writing to the t xbn register by mistake. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. 7 0 asifn 6 0 5 0 4 0 3 0 2 0 <1> txbfn <0> txsfn after reset: 00h r address: asif0 fffffa05h, asif1 fffffa15h txbfn transmit buffer data flag 0 data to be transferred next to the txbn register does not exist (when the asimn.uartcaen or asimn.txen bit is 0, or when data has been transferred to the transmit shift register) 1 data to be transferred next exists in the txbn register (data exists in the txbn register when the txbn register has been written to) ? when transmission is performed contin uously, data should be written to the txbn register after confirming that this flag is 0. if writing to the txbn register is performed when this flag is 1, transmit data cannot be guaranteed. txsfn transmit shift register data flag (indicating the transmission status of uartn) 0 initial status or awaiting transmission (when the asimn.uartcaen or asimn.txen bit is cleared to 0, or following transfer completion, the next data transmission from the txbn register is not performed) 1 transmission in progress (when data has been transferred from the txbn register) ? when the transmission unit is initialized, initialization should be executed after confirming that this flag is 0 follo wing the occurrence of a transmission completion interrupt. if initialization is performed when this flag is 1, transmit data cannot be guaranteed.
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 304 (4) receive buffer register n (rxbn) rxbn is an 8-bit buffer register for storing parallel data that had been converted by the receive shift register. when reception is enabled (asimn.rxen bit = 1), receive dat a is transferred from the receive shift register to the rxbn register, synchronized with the completion of th e shift-in processing of one frame. also, a reception completion interrupt request (intsrn) is generated by t he transfer to the rxbn register. for information about the timing for generating this interrupt request, see 14.5 (4) receive operation . if reception is disabled (asimn.rxen bit = 0), the contents of the rxbn register are retained, and no processing is performed for transferring data to the rxbn register even when the shift-in processing of one frame is completed. also, no reception completion interrupt is generated. when 7 bits is specified for the data length, bits 6 to 0 of the rxbn register are transferred for the receive data and the msb (bit 7) is always 0. however, if an overr un error (oven) occurs, the receive data at that time is not transferred to the rxbn register. except after reset, the rxbn register becomes ffh even when asimn.uartcaen = 0. this register is read-only, in 8-bit units. 7 rxbn7 rxbn 6 rxbn6 5 rxbn5 4 rxbn4 3 rxbn3 2 rxbn2 1 rxbn1 0 rxbn0 after reset: ffh r address: rxb0 fffffa02h, rxb1 fffffa12h
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 305 (5) transmit buffer register n (txbn) txbn is an 8-bit buffer register for setting transmit data. when transmission is enabled (asimn.txen bit = 1), the tr ansmit operation is started by writing data to txbn register. when transmission is disabled (asimn.txen bit = 0), even if data is written to txbn register, the value is ignored. the txbn register data is transferred to the transmit shift register, and a transmission completion interrupt request (intstn) is generated, synchr onized with the completion of the transmission of one frame from the transmit shift register. for info rmation about the timing for generating this interrupt request, see 14.5 (2) transmit operation . when asifn.txbfn bit = 1, the txbn register must not be written. this register can be read or written in 8-bit units. reset sets this register to ffh. 7 txbn7 txbn 6 txbn6 5 txbn5 4 txbn4 3 txbn3 2 txbn2 1 txbn1 0 txbn0 after reset: ffh r/w address: txb0 fffffa04h, txb1 fffffa14h
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 306 14.4 interrupt requests the following three types of interrupt requests are generated from uartn. ? reception error interrupt (intsren) ? reception completion interrupt (intsrn) ? transmission completion interrupt (intstn) the default priorities among these three types of interrupt requests is, from hi gh to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt. table 14-2. generated interrupts and default priorities interrupt priority reception error 1 reception completion 2 transmission completion 3 (1) reception error interrupt (intsren) when reception is enabled, a reception error interrupt is generated according to the logical or of the three types of reception errors explained for the asisn regist er. whether a reception erro r interrupt (intsren) or a reception completion interrupt (intsrn) is generated when an error occurs can be specified using the asimn.isrmn bit. when reception is disabled, no rec eption error interrupt is generated. (2) reception completion interrupt (intsrn) when reception is enabled, a reception completion interrupt is generated when data is shifted in to the receive shift register and transferred to the receive buffer register (rxbn). a reception completion interrupt request can be specified to be generated in place of a reception error interrupt using the asimn.isrmn bit even when a reception error has occurred. when reception is disabled, no reception completion interrupt is generated. (3) transmission completion interrupt (intstn) a transmission completion interrupt is generated when on e frame of transmit data containing 7-bit or 8-bit characters is shifted out from the transmit shift register.
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 307 14.5 operation (1) data format full-duplex serial data transmission and reception can be performed. the transmit/receive data format consis ts of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in figure 14-2. the character bit length within one data frame, the type of parity, and th e stop bit length are specified by the asimn register. also, data is transferred lsb first. figure 14-2. asynchronous serial in terface transmit/receive data format 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bits character bits ? start bit .............. 1 bit ? character bits .... 7 bits or 8 bits ? parity bit ............ even parity, odd parity, 0 parity, or no parity ? stop bits ............ 1 bit or 2 bits
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 308 (2) transmit operation when the asimn.uartcaen bit is set to 1, a high level is output from the txdn pin. then, when the asimn.txen bit is set to 1, transmission is enabled, and the transmit operation is started by writing transmit data to the txbn register. (a) transmission enabled state this state is set by the asimn.txen bit. ? txen bit = 1: transmission enabled state ? txen bit = 0: transmission disabled state since uartn does not have a cts (transmission enab led signal) input pin, a port should be used to confirm whether the destination is in a reception enabled state. (b) starting a transmit operation in the transmission enabled state, a transmit operation is started by wr iting transmit data to the txbn register. when a transmit operation is started, the data in the txbn register is transferred to the transmit shift register. then, the transmit shift register outputs data to the txdn pin (the transmit data is transferred sequentially starting with the start bit). the start bit, parity bit, and stop bits are added automatically. (c) transmission interrupt when the transmit shift register becomes empty, a transmission completion interrupt (intstn) is generated. the timing for generating the intstn interrupt differs according to the specification of the stop bit length. the intstn interrupt is generated at the same time that the last stop bit is output. if the data to be transmitted next has not been written to the txbn register, t he transmit operation is suspended. caution normally, when the transmit shift regi ster becomes empty, a transmission completion interrupt (intstn) is generated. ho wever, no transmission completion interrupt (intstn) is generated if the transmit sh ift register becomes empty due to a reset.
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 309 figure 14-3. asynchronous serial interface transmission completion interrupt timing start stop d0 d1 d2 d6 d7 parity parity txdn (output) intstn (output) start d0 d1 d2 d6 d7 txdn (output) intstn (output) (a) stop bit length: 1 (b) stop bit length: 2 stop
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 310 (3) continuous transmission operation uartn can write the next transmit data to the txbn register at the timing t hat the transmit shift register starts the shift operation. this enables an efficient transmissi on rate to be realized by continuously transmitting data even during the intstn interrupt servicing after the transmission of one data frame. in addition, reading the asifn.txsfn bit after the occurrence of a transmission comp letion interrupt enables the txbn register to be efficiently written twice (2 bytes) without wa iting for the transmission of 1 data frame. when continuous transmission is performed, data should be written after referencing the asifn register to confirm the transmission status and whether or not data can be written to the txbn register. caution the values of the asifn.txbfn and asifn.txsfn bits change 10 11 01 in continuous transmission. therefore, do not confirm the status based on the comb ination of the txbfn and txsfn bits. read only the txbfn bit during continuous transmission. txbfn whether or not writing to txbn register is enabled 0 writing is enabled 1 writing is not enabled caution when transmission is perfo rmed continuously, write the first tr ansmit data (first byte) to the txbn register and confirm that the txbfn bit is 0, and then write the next transmit data (second byte) to txbn register. if writing to the txbn register is pe rformed when the txbfn bit is 1, transmit data cannot be guaranteed. the communication status can be confir med by referring to the txsfn bit. txsfn transmission status 0 transmission is completed. 1 under transmission. cautions 1. when initializing th e transmission unit when continu ous transmission is completed, confirm that the txbfn bit is 0 after the occurrence of the tran smission completion interrupt, and then execute initialization. if initialization is perfo rmed when the txsfn bit is 1, transmit data cannot be guaranteed. 2. while transmission is bein g performed continuously, an o verrun error may occur if the next transmission is completed before th e intstn interrupt servicing following the transmission of 1 data frame is executed. an overrun error can be detected by embedding a program that can count the numbe r of transmit data and referencing the txsfn bit.
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 311 figure 14-4. continuous transmission processing flow set registers interrupt occurrence wait for interrupt required number of transfers performed? write transmit data to txbn register write transmit data to txbn register when reading asifn register, txbfn = 0? when reading asifn register, txsfn = 1? when reading asifn register, txsfn = 0? no no no no yes yes yes yes end of transmission processing
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 312 (a) starting procedure the procedure to start continuous transmission is shown below. figure 14-5. continuous transmission starti ng procedure (when stop bit length is 1) txdn (output) data (1) data (2) <5> <1> <2> <4> intstn (output) txbn register ffh ffh data (1) data (2) data (3) data (1) data (2) data (3) <3> asifn register (txbfn, txsfn bits) 00 11 note 11 01 01 11 01 11 transmit shift register start bit stop bit stop bit start bit 10 note see 14.7 cautions (2) . asifn register transmission starting procedure internal operation txbfn txsfn ? set transmission mode <1> start transmission unit 0 0 ? write data (1) 1 0 <2> generate start bit ? read asifn register (confirm that txbfn bit = 0) start data (1) transmission 1 0 0 0 1 note 1 1 1 ? write data (2) <> 1 1 <3> intstn interrupt occurs ? read asifn register (confirm that txbfn bit = 0) 0 0 1 1 ? write data (3) <4> generate start bit start data (2) transmission <> 1 1 <5> intstn interrupt occurs ? read asifn register (confirm that txbfn bit = 0) 0 0 1 1 ? write data (4) 1 1 note see 14.7 cautions (2) .
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 313 (b) ending procedure the procedure for ending continuous transmission is shown below. figure 14-6. continuous transmission end procedure (when stop bit length is 1) txdn (output) data (m ? 1) data (m) <11> <7> <6> <8> <10> intstn (output) txbn register data (m ? 1) data (m ? 1) data (m) ffh data (m) <9> asifn register (txbfn, txsfn bits) uartcaen bit or txen bit 11 01 11 01 00 transmit shift register start bit start bit stop bit stop bit asifn register transmission end procedure internal operation txbfn txsfn <6> transmission of data (m ? 2) is in progress 1 1 <7> intstn interrupt occurs ? read asifn register (confirm that txbfn bit = 0) 0 0 1 1 ? write data (m) <8> generate start bit start data (m ? 1) transmission <> 1 1 <9> intstn interrupt occurs ? read asifn register (confirm that txsfn bit = 1) there is no write data <10> generate start bit start data (m) transmission <> 0 0 1 1 <11> generate intstn interrupt ? read asifn register (confirm that txsfn bit = 0) ? clear (0) the uartcaen bit or txen bit initialize internal circuits 0 0 0 0
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 314 (4) receive operation the awaiting reception state is set by setting the asi mn.uartcaen bit to 1 and then setting the rxen bit to 1 in the asimn register. to start the receive operation, st art sampling at the falling edge when the falling of the rxdn pin is detected. if the rxdn pin is low level at a start bit sampling point, the start bit is recognized. when the receive operation begins, serial data is stored sequentially in the receive shift register according to the baud rate that was set. a reception completion inte rrupt (intsrn) is generated each time the reception of one frame of data is completed. normally, the receive da ta is transferred from the rxbn register to memory by this interrupt servicing. (a) reception enabled state the receive operation is set to the reception enabled st ate by setting the rxen bit in the asimn register to 1. ? rxen bit = 1: reception enabled state ? rxen bit = 0: reception disabled state in reception disabled state, the recept ion hardware stands by in the initia l state. at this time, the contents of the rxbn register are retained, and no reception completion interrupt or re ception error interrupt is generated. (b) starting a receive operation a receive operation is started by the detection of a start bit. the rxdn pin is sampled using the serial clock from baud rate generator n (brgn). (c) reception completion interrupt when the rxen bit = 1 and the reception of one fram e of data is completed (the stop bit is detected), a reception completion interrupt (intsrn) is generated an d the receive data within the receive shift register is transferred to the rxbn register at the same time. also, if an overrun error (oven flag) occurs, the receiv e data at that time is not transferred to the rxbn register, and either a reception completion interrupt (i ntsrn) or a reception error interrupt (intsren) is generated (the receive data within the receive shift register is transferred to rxbn) according to the asimn.isrmn bit setting. even if a parity error (pen flag) or framing error (fen flag) occurs during a reception operation, the receive operation continues until stop bit is received, and a fter reception is completed, either a reception completion interrupt (intsrn) or a reception error interrupt (intsren) is generated according to the isrmn bit setting (the receive data within the receive shi ft register is transferred to the rxbn register). if the rxen bit is cleared (0) during a receive operatio n, the receive operation is immediately stopped. the contents of the rxbn register and of the asisn register at this ti me do not change, and no reception completion interrupt (intsrn) or receptio n error interrupt (intsren) is generated. no reception completion interrupt is generated when rxen = 0 (reception is disabled).
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 315 figure 14-7. asynchronous serial interfac e reception completion interrupt timing start d0 d1 d2 d6 d7 rxdn (input) intsrn (output) rxbn register parity stop cautions 1. be sure to read the rx bn register even when a reception er ror occurs. if the rxbn register is not read, an overrun error will occur at th e next data reception and the reception error status will continue infinitely. 2. reception is always performed assuming a stop bit length of 1. a second stop bit is ignored. (5) reception error the three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. as a result of data reception, the various flags of the asisn register are set (1), and a reception error interrupt (intsren) or a recept ion completion interrupt (intsrn) is generated at the same time. the asimn.isrmn bit specifies whether intsren or intsrn is generated. the type of error that occurred during reception can be detected by reading the conten ts of the asisn register during the intsren or intsrn interrupt servicing. the contents of the asisn r egister are reset (0) by reading the asisn register. table 14-3. reception error causes error flag reception error cause pen parity error the parity specificat ion during transmission did not match the parity of the reception data fen framing error no stop bit was detected oven overrun error the reception of the next data was completed before data was read from the rxbn register
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 316 (a) separation of rece ption error interrupt a reception error interrupt can be separated from the intsrn interrupt and generated as the intsren interrupt by clearing the asimn.isrmn bit to 0. figure 14-8. when reception error interrupt is se parated from reception completion interrupt (intsrn) (isrmn bit = 0) (a) no error occurs during reception (b) an error occurs during reception intsrn (output) (reception completion interrupt) intsren (output) (reception error interrupt) intsrn (output) (reception completion interrupt) intsren (output) (reception error interrupt) intsrn does not occur figure 14-9. when reception erro r interrupt is included in reception completion interrupt (intsrn) (isrmn bit = 1) (a) no error occurs during reception (b) an error occurs during reception intsrn (output) (reception completion interrupt) intsren (output) (reception error interrupt) intsrn (output) (reception completion interrupt) intsren (output) (reception error interrupt) intsren does not occur
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 317 (6) parity types and co rresponding operation a parity bit is used to detect a bit error in communicati on data. normally, the same type of parity bit is used on the transmission and reception sides. (a) even parity (i) during transmission the parity bit is controlled so t hat the number of bits with the value ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 1 ? if the number of bits with the value ?1? within the transmit data is even: 0 (ii) during reception the number of bits with the value ?1? within the rece ive data including the parity bit is counted, and a parity error is generated if this number is odd. (b) odd parity (i) during transmission in contrast to even parity, the parit y bit is controlled so that the number of bits with the value ?1? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 0 ? if the number of bits with the value ?1? within the transmit data is even: 1 (ii) during reception the number of bits with the value ?1? within the rece ive data including the parity bit is counted, and a parity error is generated if this number is even. (c) 0 parity during transmission the parity bit is set to ?0? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ?0? or ?1?. (d) no parity no parity bit is added to the transmit data. during reception, the receive operati on is performed as if there were no parity bit. since there is no parity bit, no parity error is generated.
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 318 (7) receive data noise filter the rxdn signal is sampled at the rising edge of the prescaler output base clock (clock). if the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see figure 14-11 ). see 14.6 (1) (a) base clock (clock) regarding the base clock. also, since the circuit is configured as shown in figure 14 -10, internal processing during a receive operation is delayed by up to 2 clocks accordin g to the external signal status. figure 14-10. noise filter circuit rxdn q clock in ld_en q in internal signal a internal signal b match detector figure 14-11. timing of rxdn signal judged as noise internal signal a clock rxdn (input) internal signal b match mismatch (judged as noise) mismatch (judged as noise) match
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 319 14.6 dedicated baud rate generator n (brgn) a dedicated baud rate generator, which consists of a s ource clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by uartn. the dedicated baud ra te generator output can be selected as the serial clock for each channel. separate 8-bit counters exist fo r transmission and for reception. (1) baud rate generator n (brgn) configuration figure 14-12. configuration of baud rate generator n (brgn) f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 tom output clock (f cksr ) selector uartcaen 8-bit counter match detector baud rate brgcn: mdl7 to mdl0 1/2 uartcaen and txen (or rxen) cksrn: tps3 to tps0 f xx remark f xx : main clock frequency m = 20 when n = 0 m = 21 when n = 1 (a) base clock (clock) when the asimn.uartcaen bit = 1 the clock selected according to the cksrn.tps3 to cksrn.tps0 bits is supplied to the transmission/reception unit. this clock is called the base clock (clock), and its frequency is referred to as f cksr . when uartcaen = 0, clock is fixed to low level.
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 320 (2) serial clock generation a serial clock can be generated according to the settings of the cksrn and brgcn registers. the base clock to the 8-bit counter is select ed by the cksrn.tps3 to cksrn.tps0 bits. the 8-bit counter divisor value can be set by the brgcn.mdl7 to brgcn.mdl0 bits. (a) clock select register n (cksrn) cksrn is an 8-bit register for selecting the base clo ck using the tps3 to tps0 bits. the clock selected by the tps3 to tps0 bits becomes the base clock (clock) of the transmission/reception module. its frequency is referred to as f cksr . this register can be read or written in 8-bit units. reset sets this register to 00h. caution clear the asimn.uartcaen bit to 0 be fore rewriting the tps3 to tps0 bits. 7 0 cksrn 6 0 5 0 4 0 3 tpsn3 2 tpsn2 1 tpsn1 0 tpsn0 after reset: 00h r/w address: cksr0 fffffa06h, cksr1 fffffa16h tpsn3 tpsn2 tpsn1 tpsn0 receive operation 0 0 0 0 f xx note 0 0 0 1 f xx /2 0 0 1 0 f xx /4 0 0 1 1 f xx /8 0 1 0 0 f xx /16 0 1 0 1 f xx /32 0 1 1 0 f xx /64 0 1 1 1 f xx /128 1 0 0 0 f xx /256 1 0 0 1 f xx /512 1 0 1 0 f xx /1024 1 0 1 1 tom output other than above setting prohibited remark m = 20 when n = 0 m = 21 when n = 1 note setting the tpsn3 to tpsn0 bits to 0000b is prohibited when v dd < 3.0 v and f xx > 10 mhz.
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 321 (b) baud rate generator c ontrol register n (brgcn) brgcn is an 8-bit register that controls t he baud rate (serial transfer speed) of uartn. this register can be read or written in 8-bit units. reset sets this register to ffh. caution if the mdln7 to mdln0 bits are to be overwritten, the asimn.txen and asimn.rxen bits should be cleared to 0 first. 7 mdln7 brgcn 6 mdln6 5 mdln5 4 mdln4 3 mdln3 2 mdln2 1 mdln1 0 mdln0 after reset: ffh r/w address: brgc0 fffffa07h, brgc1 fffffa17h md ln7 md ln6 md ln5 md ln4 md ln3 md ln2 md ln1 md ln0 setting value (k) serial clock 0 0 0 0 0 ? setting prohibited 0 0 0 0 1 0 0 0 8 f cksr /8 0 0 0 0 1 0 0 1 9 f cksr /9 0 0 0 0 1 0 1 0 10 f cksr /10 : : : : : : : : : : 1 1 1 1 1 0 1 0 250 f cksr /250 1 1 1 1 1 0 1 1 251 f cksr /251 1 1 1 1 1 1 0 0 252 f cksr /252 1 1 1 1 1 1 0 1 253 f cksr /253 1 1 1 1 1 1 1 0 254 f cksr /254 1 1 1 1 1 1 1 1 255 f cksr /255 remarks 1. f cksr : frequency [hz] of base clock (clock) select ed by cksrn.tpsn3 to cksrn.tpsn0 bits. 2. k: value set by mdln7 to mdln0 bits (k = 8, 9, 10, ..., 255) 3. the baud rate is the output clock fo r the 8-bit counter divided by 2 4. : don?t care
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 322 (c) baud rate the baud rate is the value obtained by the following formula. [bps] k 2 f rate baud cksr = f cksr = frequency [hz] of base clock (clock) sele cted by cksrn.tpsn3 to cksrn.tpsn0 bits. k = value set by brgcn.mdln7 to brgcn. mdln0 bits. (k = 8, 9, 10, ..., 255) (d) baud rate error the baud rate error is obtained by the following formula. error (%) = ? 1 100[%] cautions 1. make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination. 2. make sure that the baud rate error duri ng reception is within the allowable baud rate range described in (4) allowable baud rate range dur ing reception. example: base clock (clock) frequency = 20 mhz = 20,000,000 hz setting of brgcn.mdln7 to brgcn.mdln0 bits = 01000001b (k = 65) target baud rate = 153,600 bps baud rate = 20m/(2 65) = 20,000,000/(2 65) = 153,846 [bps] error = (153,846/153,600 ? 1) 100 = 0.160 [%] actual baud rate (baud rate with error) target baud rate (normal baud rate)
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 323 (3) baud rate setting example table 14-3. baud rate generator setting data f xx = 20 mhz f xx = 10 mhz baud rate [bps] f cksr k err f cksr k err 300 f xx /512 65 0.16 f xx /256 65 0.16 600 f xx /256 65 0.16 f xx /128 65 0.16 1,200 f xx /128 65 0.16 f xx /64 65 0.16 2,400 f xx /64 65 0.16 f xx /32 65 0.16 4,800 f xx /32 65 0.16 f xx /16 65 0.16 9,600 f xx /16 65 0.16 f xx /8 65 0.16 19,200 f xx /8 65 0.16 f xx /4 65 0.16 31,250 f xx /32 10 0.00 f xx /16 10 0.00 38,400 f xx /4 65 0.16 f xx /2 65 0.16 76,800 f xx /2 65 0.16 f xx 65 0.16 153,600 f xx 65 0.16 f xx 33 ? 1.36 312,500 f xx /4 8 0.00 f xx /2 8 0.00 remark f xx : main clock frequency f cksr : base clock frequency k: setting values of brgcn.mdln7 to brgcn.mdln0 bits err: baud rate error [%]
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 324 (4) allowable baud rate range during reception the degree to which a discrepancy from the transmission de stination?s baud rate is allowed during reception is shown below. caution the equations desc ribed below should be used to set th e baud rate error during reception so that it always is within the allowable error range. figure 14-13. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartn transfer rate latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 14-13, after the start bit is detected, the receive data latch timi ng is determined according to the counter that was set by the brgcn register. if all da ta up to the final data (stop bit) is in time for this latch timing, the data can be received normally. if this is applied to 11-bit reception, the following is theoretically true. fl = (brate) ?1 brate: uartn baud rate k: brgcn register setting value fl: 1-bit data length when the latch timing margin is 2 base clocks (clock) , the minimum allowable transfer rate (flmin) is as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 flmin + = ? ? =
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 325 therefore, the transfer destination?s maximum re ceivable baud rate (brmax) is as follows. brate 2 k 21 22k (flmin/11) brmax 1 + = = ? similarly, the maximum allowable transfer rate (flmax) can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 flmax 11 10 ? = + ? = 11 fl k 20 2 k 21 flmax ? = therefore, the transfer destination?s minimum receivable baud rate (brmin) is as follows. brate 2 k 21 20k (flmax/11) brmin 1 ? = = ? the allowable baud rate error of uartn and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. table 14-4. maximum and minimum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 8 +3.53% ?3.61% 20 +4.26% ?4.31% 50 +4.56% ?4.58% 100 +4.66% ?4.67% 255 +4.72% ?4.73% remarks 1. the reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). the higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: brgcn register setting value
chapter 14 asynchronous serial interface n (uartn) user?s manual u16237ej3v0ud 326 (5) transfer rate durin g continuous transmission during continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock (clock) longer than normal. however, on t he reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit. figure 14-14. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame bit 0 fl fl fl fl fl fl flstp start bit of second byte start bit representing the 1-bit data length by fl, the stop bi t length by flstp, and the base clock frequency by f cksr yields the following equation. flstp = fl + 2/f cksr therefore, the transfer rate during continuous tr ansmission is as follows (when stop bit length = 1). transfer rate = 11 fl = 2/f cksr 14.7 cautions cautions to be observed when using uartn are shown below. (1) when the supply of clocks to uartn is stopped (for example, in idle or stop mode), operation stops with each register retaining the value it had immediately befo re the supply of clocks was stopped. the txdn pin output also holds and outputs the value it had immediat ely before the supply of clocks was stopped. however, operation is not guaranteed after the supply of clocks is restarted. therefore, after the supply of clocks is restarted, the circuits should be initialized by setting the asimn.uartcaen, asimn.rxen, and asimn.txen bits = 000 in register. (2) uartn has a 2-stage buffer configur ation consisting of the txbn regist er and the transmit shift register, and has status flags (the asifn.txbfn and asifn .txsfn bits) that indicate the stat us of each buffer. if the txbfn and txsfn bits are read in continuous tr ansmission, the value changes from 10 11 01. read only the txbfn bit during continuous transmission.
user?s manual u16237ej3v0ud 327 chapter 15 clocked serial interface n (csin) 15.1 features ? transfer rate: master mode: maximum 5 mbps (w hen internal system clock operates at 20 mhz) slave mode: maximum 5 mbps ? half-duplex communications ? master mode and slave mode can be selected ? transmission data length: 8 bits ? transfer data direction can be switched between msb first and lsb first ? seven clock signals can be selected (6 master clocks and 1 slave clock) ? 3-wire method ? son: serial data output ? sin: serial data input ? sckn: serial clock input/output ? interrupt sources: 1 type ? transmission/reception completion interrupt (intcsin) ? transmission/reception mode or recept ion-only mode can be specified ? on-chip transmit buffer (sotbn) remark n = 0, 1 15.2 configuration csin is controlled by the clocked serial interface mode regi ster (csimn). transmit/receive data can be written to or read from the sion register. (1) clocked serial interface mode register n (csimn) csimn is an 8-bit register for s pecifying the operation of csin. (2) clocked serial interface cloc k select register n (csicn) csicn is an 8-bit register for contro lling the transmit operation of csin. (3) serial i/o shift register n (sion) sion is an 8-bit register for converting between serial da ta and parallel data. the sion register is used for both transmission and reception. data is shifted in (reception) or shifted out (transmissi on) beginning at either the msb side or the lsb side. actual transmit/receive operations are controll ed by reading or writing the sion register. (4) clocked serial interface transm it buffer register n (sotbn) sotbn is an 8-bit buffer register for storing transmit data. (5) selector the selector selects the serial clock to be used.
chapter 15 clocked serial interface n (csin) user?s manual u16237ej3v0ud 328 (6) serial clock controller the serial clock controller co ntrols the supply of serial clocks to the shift register. when an internal clock is used, it also controls the clocks that are output to the sckn pin. (7) serial clock counter the serial clock counter counts serial clocks that ar e output or input during transmit and receive operations and checks that 8-bit data has been transmitted or received. (8) interrupt controller the interrupt controller controls w hether or not an interrupt request is generated when the serial clock counter has counted eight serial clocks. figure 15-1. clocked seri al interface block diagram selector cksn0 to cksn2 intcsin csotn son transfer clock controller transfer mode controller transfer data controller transmit buffer (sotbn) selector son latch sin sckn shift register (sion) f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 tom csien, trmdn, dirn, ckpn, dapn remarks 1. m = 20 when n = 0 m = 21 when n = 1 2. f xx : main clock frequency
chapter 15 clocked serial interface n (csin) user?s manual u16237ej3v0ud 329 15.3 registers (1) clocked serial interface mode register n (csimn) csimn is a register that cont rols the operation of csin. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution to use csin, be sure to se t the external pins related to the csin function to control mode and set the csicn register. then set the csien bit to 1 before setting the other bits. remark n = 0, 1 csien csin operation is disabled (son = low level, sckn = high level) csin operation is enabled csien 0 1 csin operation enable/disable specification csimn trmdn 0 dirn 0 0 0 csotn after reset: 00h r/w address: csim0 fffffd00h, csim1 fffffd10h ? if csien is set to 0, the csin unit can be reset note asynchronously. ? if csien = 0, the csin unit is in a reset state. therefore, to operate csin, csien must be set to 1. ? if the csien bit is changed from 1 to 0, all registers of the csin unit are initialized. to set csien to 1 again, the registers of the csin unit must be set again. reception-only mode transmission/reception mode trmdn 0 1 transmission mode specification ? if trmdn = 0, reception mode is selected. in addition, son outputs a low level. data reception is started by reading the sion register. if trmdn = 1, transmission/reception is started by writing data to the sotbn register. ? the trmdn bit can be overwritten only when csotn = 0. msb first lsb first dirn 0 1 transfer direction mode (msb/lsb specification) ? the dirn bit can be overwritten only when csotn = 0. communication stopped communication in progress csotn 0 1 communication status flag ? this flag is used to judge whether writing to the sion register is enabled or not when starting serial data transmission in transmission/reception mode (trmdn = 1) ? the csotn bit is cleared when the csie bit is cleared (0). <7> <0> <6> <4> note the following registers and bit can be reset. sion and sioen registers csimn.csotn bit caution be sure to clear bits 5 and 3 to 1 to ?0?. remark n = 0, 1
chapter 15 clocked serial interface n (csin) user?s manual u16237ej3v0ud 330 (2) clocked serial interface cloc k select register n (csicn) csicn is an 8-bit register that cont rols the transmit operation of csin. this register can be read or written in 8-bit units. reset sets this register to 00h. caution the csicn register can only be overwr itten after csimn.csien is cleared to 0. 0 ckpn 0 0 1 1 specification of data transmission/reception timing for sckn csicn 0 dapn 0 1 0 1 0 ckpn dapn cksn2 cksn1 cksn0 after reset: 00h r/w address: csic0 fffffd01h, csic1 fffffd11h cksn2 0 0 0 0 1 1 1 1 cksn1 0 0 1 1 0 0 1 1 cksn0 0 1 0 1 0 1 0 1 serial clock setting prohibited f xx /4 note 1 f xx /8 f xx /16 f xx /32 f xx /64 tom output note 2 external clock (sckn) master mode master mode master mode master mode master mode master mode slave mode mode d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) notes 1. setting is prohibited when v dd < 3.0 v and f xx > 10 mhz. 2. m = 20 when n = 0 m = 21 when n = 1
chapter 15 clocked serial interface n (csin) user?s manual u16237ej3v0ud 331 (a) transfer rate selection example transfer rate (bps) cksn2 cksn1 cksn0 20 mhz operation 10 mhz operation 0 0 0 setting prohibited setting prohibited 0 0 1 5,000,000 note 2,500,000 0 1 0 2,500,000 1,250,000 0 1 1 1,250,000 625,000 1 0 0 625,000 312,500 1 0 1 312,500 156,250 note setting is prohibited when 2.7 v v dd < 3.0 v. (3) serial i/o shift register n (sion) sion is an 8-bit shift register that converts parallel data to serial data. if csimn.trmdn = 0, the receive operation is started by r eading the sion register. except after reset, the sion register becomes 00h even when the csimn.csien bit is cleared (0). sion shifts data in (reception) or shifts data out (transmission) beginning at the msb or the lsb side. this register is read-only, in 8-bit units. caution the sion register can be accessed only when the system is in an idle state (csimn.csotn bit = 0). sion7 sion sion6 sion5 sion4 sion3 sion2 sion1 sion0 after reset: 00h r address: sio0 fffffd02h, sio1 fffffd12h remark n = 0, 1
chapter 15 clocked serial interface n (csin) user?s manual u16237ej3v0ud 332 (4) receive-only serial i/o shift register n (sioen) sioen is an 8-bit shift register that converts parallel da ta into serial data. a receive operation does not start even if the sioen register is read while the csimn.trmdn bi t is 0. therefore this register is used to read the value of the sion register (receive da ta) without starting a receive operation. sioen shifts data in (reception) beg inning at the msb or the lsb side. except after reset, the sioen register becomes 00h even when the csimn.csien bit is cleared (0). this register is read-only, in 8-bit units. caution the sioen register can be accessed only when the system is in an idle state (csimn.csotn bit = 0). sioen7 sioen sioen6 sioen5 sioen4 sioen3 sioen2 sioen1 sioen0 after reset: 00h r address: sioe0 fffffd03h, sioe1 fffffd13h remark n = 0, 1 (5) clocked serial interface transm it buffer register n (sotbn) sotbn is an 8-bit buffer register for storing transmit data. if transmission/reception mode is set (csimn.trmdn = 1), a transmit operation is started by writing data to the sotbn register. this register can be read or written in 8-bit units. reset sets this register to 00h. caution the sotbn register can be accessed only when the system is in an idle state (csimn.csotn bit = 0). sotbn7 sotbn sotbn6 sotbn5 sotbn4 sotbn3 sotbn2 sotbn1 sotbn0 after reset: 00h r/w address: sotb0 fffffd04h, sotb1 fffffd14h remark n = 0, 1
chapter 15 clocked serial interface n (csin) user?s manual u16237ej3v0ud 333 15.4 operation (1) transfer mode csin transmits and receives data using three lines: 1 clock line and 2 data lines. in reception-only mode (csimn.trmdn = 0), the communication is started by reading the sion register. to read the value of the sion r egister without starting receptio n, read the sioen register. in transmission/reception mode (csimn.trmdn = 1), t he communication is started by writing data to the sotbn register. when an 8-bit transfer of csin ends, the csimn.csotn bit becomes 0, and transfer stops automatically. also, when the transfer ends, a transmission/recepti on completion interrupt (intcsin) is generated. cautions 1. when csimn.csotn bit = 1, the cont rol registers and data registers should not be accessed. 2. if transmit data is written to the sotb n register and the csimn.trmdn bit is changed from 0 to 1, serial transfer is not performed. remark n = 0, 1 (2) serial clock (a) when internal clock is selected as the serial clock if reception or transmission is started, a serial clock is output from the sckn pin, and the data of the sin pin is taken into the sion register sequentially or dat a is output to the son pin sequentially from the sion register when the data is synchro nized with the serial clock in accordance with the setting of the csicn.ckpn and csicn.dapn bits. (b) when external clock is selected as the serial clock if reception or transmission is started, the data of the sin pin is taken into the sion register sequentially or output to the son pin sequentially in synchronization wit h the serial clock that has been input to the sckn pin following transmission/reception startup in a ccordance with the setting of the csicn.ckpn and csicn.dapn bits. if serial clock is input to the sckn pin when neither reception nor transmission is started, a shift operation will not be executed. remark n = 0, 1
chapter 15 clocked serial interface n (csin) user?s manual u16237ej3v0ud 334 figure 15-2. transfer timing (a) when trmdn = 1, dirn = 0, ckpn = 0, and dapn = 0 10101010 1 0101010 (aah) (55h) (write 55h to sotbn) 55h (transmission data) csotn bit sckn reg-r/w sotbn sion sin son intcsin interrupt abh 56h adh b5h 6ah d5h aah 5ah remark n = 0, 1 (b) when trmdn = 1, dirn = 0, ckpn = 0, and dapn = 1 10101010 1 0101010 (aah) (55h) (write 55h to sotbn) 55h (transmission data) csotn bit sckn reg-r/w sotbn sion sin son intcsin interrupt abh 56h adh b5h 6ah d5h aah 5ah remark n = 0, 1
chapter 15 clocked serial interface n (csin) user?s manual u16237ej3v0ud 335 figure 15-3. clock timing (a) when ckpn = 0 and dapn = 0 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 (b) when ckpn = 1 and dapn = 0 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 (c) when ckpn = 0 and dapn = 1 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 (d) when ckpn = 1 and dapn = 1 intcsin interrupt sin capture sckn sion reg-r/w csotn bit d7 d6 d5 d4 d3 d2 d1 d0 remark n = 0, 1
chapter 15 clocked serial interface n (csin) user?s manual u16237ej3v0ud 336 15.5 output pins the output pins are described below. for the setting of each pin, see table 4-15 settings when port pins are used for alternate functions . (1) sckn pin when csin operation is disabled (csimn.csien bit = 0), the sckn pin output state is as follows. ckpn sckn pin output 0 fixed to high level 1 fixed to low level remark n = 0, 1 (2) son pin when csin operation is disabled (csien bit = 0), the son pin output state is as follows. trmdn dapn dirn son pin output 0 fixed to low level 0 son latch value (low level) 0 sotbn7 value 1 1 1 sotbn0 value remarks 1. n = 0, 1 2. : don?t care
chapter 15 clocked serial interface n (csin) user?s manual u16237ej3v0ud 337 15.6 system configuration example csin performs 8-bit length data transfer using three signal lines: a serial clock (sckn), serial input (sin), and serial output (son). this is effective when connecting peripheral i/o that incorporate a conventional clocked serial interface, or a display controller to the v850es/pm1 (n = 0, 1). when connecting the v850es/pm1 to several devices, lines for handshake are required. since the first communication bit can be selected as msb or lsb, communication with various devices can be achieved. figure 15-4. system configuration example of csi sck master cpu slave cpu (3-wire serial i/o 3-wire serial i/o) so si port (interrupt) port si so port port (interrupt) sck
user?s manual u16237ej3v0ud 338 chapter 16 interrupt/except ion processing function the v850es/pm1 is provided with a dedica ted interrupt controller (intc) for in terrupt servicing and can process a total of 32 interrupt requests. an interrupt is an event that occurs independently of program execution, and an ex ception is an event whose occurrence is dependent on program execution. the v850es/pm1 can process interrupt requests from t he on-chip peripheral hardware and external sources. moreover, exception processing can be st arted by the trap instruction (softwar e exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). 16.1 features interrupts  non-maskable interrupts: 1 source  maskable interrupts: external: 3, internal: 28 sources  8 levels of programmable priorities (maskable interrupts)  multiple interrupt control according to priority  masks can be specified for eac h maskable interrupt request.  noise elimination, edge detection, and valid edge specification for external interrupt request signals. exceptions  software exceptions: 32 sources  exception trap: 2 sources (illegal opcode exception, debug trap) interrupt/exception sources are listed in table 16-1.
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 339 table 16-1. interrupt/exception source list (1/2) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register reset pin input pin reset interrupt ? reset wdt overflow (wdtres) wdt 0000h 00000000h undefined ? non- maskable interrupt ? nmi nmi pin valid edge input pin 0010h 00000010h nextpc ? ? trap0n note trap instruction ? 004nh note 00000040h nextpc ? software exception exception ? trap1n note trap instruction ? 005nh note 00000050h nextpc ? exception trap exception ? ilgop/ dbtrap illegal opcode/ dbtrap instruction ? 0060h 00000060h nextpc ? 0 intwdtm interval timer overfl ow wdt 0080h 00000080h nextpc wdtic 1 intp0 intp0 pin valid edge input pin 0090h 00000090h nextpc pic0 2 intp1 intp1 pin valid edge input pin 00a0h 000000a0h nextpc pic1 3 intp2 intp2 pin valid edge input pin 00b0h 000000b0h nextpc pic2 4 intad ad conversion completion adc 00c0h 000000c0h nextpc adic 5 intrtc rtc interrupt rtc 00d0h 000000d0h nextpc rtcic 6 inttm000 tm00-cr000 match/ ti001 pin input tm00 00e0h 000000e0h nextpc tmic000 7 inttm001 tm00-cr001 match/ ti000 pin input tm00 00f0h 000000f0h nextpc tmic001 8 inttm010 tm01-cr010 match/ ti011 pin input tm01 0100h 00000100h nextpc tmic010 9 inttm011 tm01-cr011 match/ ti010 pin input tm01 0110h 00000110h nextpc tmic011 10 inttm020 tm02-cr020 match/ ti021 pin input tm02 0120h 00000120h nextpc tmic020 11 inttm021 tm02-cr021 match/ ti020 pin input tm02 0130h 00000130h nextpc tmic021 12 inttm030 tm03-cr030 match/ ti031 pin input tm03 0140h 00000140h nextpc tmic030 13 inttm031 tm03-cr031 match/ ti030 pin input tm03 0150h 00000150h nextpc tmic031 14 intcc100 cc100 capture trigger input/ tm10-cc100 match tm10 0160h 00000160h nextpc ccic100 15 intcc101 cc101 capture trigger input/ tm10-cc101 match tm10 0170h 00000170h nextpc ccic101 maskable interrupt 16 intovf10 tm10 overflow tm10 0180h 00000180h nextpc ovfic10 note n = 0 to fh
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 340 table 16-1. interrupt/exception source list (2/2) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 17 intcc110 cc110 capture trigger input/ tm11-cc110 match tm11 0190h 00000190h nextpc ccic110 18 intcc111 cc111 capture trigger input/ tm11-cc111 match tm11 01a0h 000001ah nextpc ccic111 19 intovf11 tm11 overflow tm11 01b0h 000001b0h nextpc ovfic11 20 inttm20 tm20-cr20 match/ tm20 overflow tm20 01c0h 000001c0h nextpc tmic20 21 inttm21 tm21-cr21 match/ tm21 overflow tm21 01d0h 000001d0h nextpc tmic21 22 intcsi0 csi0 transfer completion csi0 01e0h 000001e0h nextpc csiic0 23 intcsi1 csi1 transfer completion csi1 01f0h 000001f0h nextpc csiic1 24 intsre0 uart0 reception error uart0 0200h 00000200h nextpc sreic0 25 intsr0 uart0 reception comple tion uart0 0210h 00000210h nextpc sric0 26 intst0 uart0 transmission completion uart0 0220h 00000220h nextpc stic0 27 intsre1 uart1 reception error uart1 0230h 00000230h nextpc sreic1 28 intsr1 uart1 reception comple tion uart1 0240h 00000240h nextpc sric1 29 intst1 uart1 transmission completion uart1 0250h 00000250h nextpc stic1 maskable interrupt 30 introv rtc overflow rt c 0260h 00000260h nextpc rovic remarks 1. default priority: the priority order when two or more maskable interrupt requests occur at the same time. the highest priority is 0. restored pc: the value of the program count er (pc) saved to eipc, fepc, or dbpc when interrupt servicing is started. note, however, that the restored pc when a non- maskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextpc (if an interrupt is acknowledged during instruction execution, execution stops, and then resumes after the interrupt servicing has finished). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? division instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only if an interrupt is generated before the stack pointer is updated) nextpc: the pc value that starts the proc essing following interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4).
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 341 16.2 non-maskable interrupts a non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (di) status. an nmi is not subject to priority control and takes precedence ov er all the other interrupts. the non-maskable interrupt request is input from the nmi pin. the valid edge of the nmi pin can be selected from four types: ?rising edge? , ?falling edge?, ?both edges?, and ?no edge detection?. if a new nmi request is issued while a nmi is being serviced, the new nmi request is held pending, regardless of the value of the np bit of the program status word (psw ) in the cpu. the pending nmi interrupt is acknowledged after the nmi currently under execution has been serv iced (after the reti instruction has been executed). caution if a non-maskable interrupt request is genera ted, the values of the pc and psw are saved to the nmi status save registers (fepc and fepsw). ex ecution can be returned from the nmi servicing by the reti instruction. figure 16-1. non-maskable interrupt request acknowledgment operation case in which new non-maskable interrupt (nmi) occurs while a non-maskable interrupt (nmi) is being serviced main routine nmi request nmi servicing (held pending) servicing of pending nmi nmi request
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 342 16.2.1 operation if a non-maskable interrupt is generated by nmi input, th e cpu performs the following processing, and transfers control to the handler routine. <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes exception code 0010h to the higher halfword (fecc) of ecr. <4> sets the psw.np and psw.id bits (1) and clears the psw.ep bit (0). <5> sets the handler address (00000010h) corresponding to the non-maskable interrupt to the pc, and transfers control. the servicing configuration of a non-maska ble interrupt is shown in figure 16-2. figure 16-2. servicing configurat ion of non-maskable interrupt psw.np fepc fepsw ecr.fecc psw.np psw.ep psw.id pc restored pc psw 0010h 1 0 1 00000010h 1 0 nmi input non-maskable interrupt request interrupt servicing interrupt request held pending intc acknowledged cpu processing
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 343 16.2.2 restore execution is restored from the nmi by the reti instruction. when the reti instruction is executed, the cpu performs the following processing, and transfers control to the address of the restored pc. <1> loads the restored pc and psw fr om fepc and fepsw, respectively, be cause the psw.ep bit is 0 and the psw.np bit is 1. <2> transfers control back to the address of the restored pc and psw. figure 16-3 illustrates how the reti instruction is processed. figure 16-3. reti instruction processing psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw caution when the psw.ep bit an d psw.np bit are changed by th e ldsr instruction during non- maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw .ep back to 0 and psw.np back to 1 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow.
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 344 16.2.3 np flag the np flag is a status flag that indicates that non -maskable interrupt servicing is under execution. this flag is set when a non-maskable interrupt request has been acknowledged, and masks non-maskable interrupt requests to prohibit multiple interrupts from being acknowledged. 0 np ep id sat cy ov s z psw no non-maskable interrupt servicing non-maskable interrupt currently being serviced np 0 1 non-maskable interrupt servicing status after reset: 00000020h
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 345 16.3 maskable interrupts maskable interrupt requests can be masked by interrupt control registers. the v850es/pm1 has 31 maskable interrupt sources. if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control). when an interrupt request has been acknowledged, the acknow ledgment of other maskable interrupt requests is disabled and the interrupt disabled (di) status is set. when the ei instruction is executed in an interrupt service routine, the interr upt enabled (ei) status is set, which enables servicing of interrupts having a higher priority than the interrupt request in progress (specified by the interrupt control register). note that only in terrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. to enable multiple interrupts, however, save eipc and eipsw to memory or registers before executing the ei instruction, and execute the di instruction before the reti instruction to restore the original values of eipc and eipsw. 16.3.1 operation if a maskable interrupt occurs by int input, the cpu perfor ms the following processing, and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower halfword of ecr (eicc). <4> sets the psw.id bit (1) and clears the psw.ep bit (0). <5> sets the handler address corresponding to each interrupt to the pc, and transfers control. the maskable interrupt request masked by intc and th e maskable interrupt request generated while another interrupt is being serviced (while psw.np = 1 or psw.id = 1) are held pending inside intc. in this case, servicing a new maskable interrupt is started in acco rdance with the priority of the pending ma skable interrupt request if either the maskable interrupt is unmasked or psw.np and psw.id are cl eared to 0 by using the reti or ldsr instruction. how maskable interrupts are serviced is illustrated below.
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 346 figure 16-4. maskable interrupt servicing int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc accepted yes yes yes priority higher than that of interrupt currently being serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address note for the ispr register, see 16.3.6 in-service priority register (ispr) . the int input masked by the interrupt controllers and the int input that occurs while another interrupt is being serviced (when psw.np = 1 or psw.id = 1) are held pending intern ally by the interrupt controll er. in such case, if the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 as set by the reti and ldsr instructions, input of the pending int starts the new maskable interrupt servicing.
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 347 16.3.2 restore recovery from maskable interrupt servicing is carried out by the reti instruction. when the reti instruction is executed , the cpu performs the following steps, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from eipc and ei psw because the psw.ep bit is 0 and the psw.np bit is 0. <2> transfers control to the address of the restored pc and psw. figure 16-5 illustrates the proce ssing of the reti instruction. figure 16-5. reti instruction processing psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw note for the ispr register, see 16.3.6 in-service priority register (ispr) . caution when the psw.ep bit an d the psw.np bit are changed by the ldsr instruction during maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw .ep back to 0 and psw.np back to 0 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow.
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 348 16.3.3 priorities of maskable interrupts the v850es/pm1 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority level c ontrol: control based on the default pr iority levels, and control based on the programmable priority levels that are spec ified by the interrupt priority level s pecification bit (xxprn) of the interrupt control register (xxicn). when two or more interrupts hav ing the same priority level specified by the xxprn bit are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. for more information, see table 16-1 interrupt source list . the programmable priority control customizes interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request is acknowledged, the id flag of psw is automatically set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 bef orehand (for example, by plac ing the ei instruction in the interrupt service program) to set the interrupt enable mode. remark xx: identification name of each peripheral unit (see table 16-2 ) n: peripheral unit number (see table 16-2 ).
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 349 figure 16-6. example of processing in whic h another interrupt request is issued while an interrupt is being serviced (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b servicing of c interrupt request c (level 3) servicing of d servicing of e ei interrupt request e (level 2) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution to perform multiple interrupt servicing, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to u in the figure are the temporary names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests.
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 350 figure 16-6. example of processing in whic h another interrupt request is issued while an interrupt is being serviced (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. caution to perform multiple interrupt servicing, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. notes 1. lower default priority 2. higher default priority
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 351 figure 16-7. example of servicing inte rrupt requests simultaneously generated default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) servicing of interrupt request b . . servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. caution to perform multiple interrupt servicing, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to c in the figure are the temporary names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests.
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 352 16.3.4 interrupt control register (xxicn) an interrupt control register is assigned to each in terrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 47h. caution read the xxicn.xxifn bit while interrupts are di sabled (di status). if the xxifn bit is read while interrupts are enabled (ei status), and if acknowle dging an interrupt conflic ts with reading the bit, the correct value of the bit may not be read. xxifn interrupt request not issued interrupt request issued xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 interrupt servicing enabled interrupt servicing disabled (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest). specifies level 1. specifies level 2. specifies level 3. specifies level 4. specifies level 5. specifies level 6. specifies level 7 (lowest). xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff110h to fffff14ch <6> <7> <1> <2> <0> note the flag xxlfn is reset automatically by the ha rdware if an interrupt request is acknowledged. remark xx: identification name of each peripheral unit (see table 16-2 ) n: peripheral unit number (see table 16-2 ). the addresses and bits of the interrupt control registers are as follows.
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 353 table 16-2. interrupt control register (xxicn) bit address register <7> <6> 5 4 3 2 1 0 fffff110h wdtic wdtif wdtmk 0 0 0 wdtpr2 wdtpr1 wdtpr0 fffff112h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff114h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff116h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff118h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff11ah rtcic rtcif rtcmk 0 0 0 rtcpr2 rtcpr1 rtcpr0 fffff11ch tmic000 tmif000 tmmk000 0 0 0 tmpr0002 tmpr0001 tmpr0000 fffff11eh tmic001 tmif001 tmmk001 0 0 0 tmpr0012 tmpr0011 tmpr0010 fffff120h tmic010 tmif010 tmmk010 0 0 0 tmpr0102 tmpr0101 tmpr0100 fffff122h tmic011 tmif011 tmmk011 0 0 0 tmpr0112 tmpr0111 tmpr0110 fffff124h tmic020 tmif020 tmmk020 0 0 0 tmpr0202 tmpr0201 tmpr0200 fffff126h tmic021 tmif021 tmmk021 0 0 0 tmpr0212 tmpr0211 tmpr0210 fffff128h tmic030 tmif030 tmmk030 0 0 0 tmpr0302 tmpr0301 tmpr0300 fffff12ah tmic031 tmif031 tmmk031 0 0 0 tmpr0312 tmpr0311 tmpr0310 fffff12ch ccic100 ccif100 ccmk100 0 0 0 ccpr1002 ccpr1001 ccpr1000 fffff12eh ccic101 ccif101 ccmk101 0 0 0 ccpr1012 ccpr1011 ccpr1010 fffff130h ovfic10 ovfif10 ovfmk10 0 0 0 ovfpr102 ovfpr101 ovfpr100 fffff132h ccic110 ccif110 ccmk110 0 0 0 ccpr1102 ccpr1101 ccpr1100 fffff134h ccic111 ccif111 ccmk111 0 0 0 ccpr1112 ccpr1111 ccpr1110 fffff136h ovfic11 ovfif11 ovfmk11 0 0 0 ovfpr112 ovfpr111 ovfpr110 fffff138h tmic20 tmif20 tmmk20 0 0 0 tmpr202 tmpr201 tmpr200 fffff13ah tmic21 tmif21 tmmk21 0 0 0 tmpr212 tmpr211 tmpr210 fffff13ch csiic0 csiif0 csimk0 0 0 0 csipr02 csipr01 csipr00 fffff13eh csiic1 csiif1 csimk1 0 0 0 csipr12 csipr11 csipr10 fffff140h sreic0 sreif0 sremk0 0 0 0 srepr02 srepr01 srepr00 fffff142h sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff144h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff146h sreic1 sreif1 sremk1 0 0 0 srepr12 srepr11 srepr10 fffff148h sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff14ah stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff14ch rovic rovif rovmk 0 0 0 rovpr2 rovpr1 rovpr0
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 354 16.3.5 interrupt mask registers 0, 1 (imr0, imr1) these registers set the interrupt mask state for the maska ble interrupts. the xxmkn bit of the imr0 and imr1 registers is equivalent to the xxicn.xxmkn bit. the imrm register can be read or written in 16-bit units (m = 0, 1). if the higher 8 bits of the imrm register are used as an imrmh register and the lower 8 bits as an imrml register, these registers can be read or written in 8-bit or 1-bit units (m = 0, 1). reset sets this register to ffffh. caution the device file defines the xxi cn.xxmkn bit as a reserved word. if a bit is manipulated using the name of xxmkn, the contents of th e xxicn register, instead of the imrm register, are rewritten (as a result, the contents of the imrm register are also rewritten). ccmk101 tmmk001 imr0 ccmk100 tmmk000 tmmk031 rtcmk tmmk030 admk tmmk021 pmk2 tmmk020 pmk1 tmmk011 pmk0 tmmk010 wdtmk after reset: ffffh r/w address: fffff100h after reset: ffffh r/w address: fffff102h 1 csimk1 imr1 rovmk csimk0 stmk1 tmmk21 srmk1 tmmk20 sremk1 ovfmk11 stmk0 ccmk111 srmk0 ccmk110 sremk0 ovfmk10 xxmkn 0 1 interrupt servicing enabled. interrupt servicing disabled. 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 setting of interrupt mask flag note be sure to set bit 15 of the imr1 register to ?1?. remark xx: identification name of each peripheral unit (see table 16-2 ) n: peripheral unit number (see table 16-2 )
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 355 16.3.6 in-service priority register (ispr) this register holds the priority level of the maskable inte rrupt currently acknowledged. when an interrupt request is acknowledged, the bit of this register corresponding to the prio rity level of that interrupt request is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, the bit corresponding to the interrupt request having the highest priority is automatically reset to 0 by hardware. however, it is not reset to 0 when execution is returned from non-maskable interrupt servicing or exception processing. this register is read-only in 8-bit or 1-bit units. reset sets this register to 00h. caution if an interrupt is acknowledged in the inte rrupt enabled (ei) status while the ispr register is being read, the value of the ispr re gister after the bit of the regist er has been set by the interrupt may be read. to accurately read the value of the ispr register before the interrupt is acknowledged, read the register in the interrupt disabled (di) status. ispr7 interrupt request with priority n not acknowledged interrupt request with priority n acknowledged isprn 0 1 priority of interrupt currently acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah <7> <6> <5> <4> <3> <2> <1> <0> remark n = 0 to 7 (priority level)
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 356 16.3.7 id flag this flag controls the maskable interr upt?s operating state, and st ores control information regarding enabling or disabling of interrupt requests. an interrupt disable fl ag (id) is incorporated, which is assigned to the psw. reset sets this register to 00000020h. 0 np ep id sat cy ov s z psw maskable interrupt request acknowledgment enabled maskable interrupt request acknowledgment disabled (pending) id 0 1 maskable interrupt servicing specification note after reset: 00000020h note interrupt disable flag (id) function this bit is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instru ction when referencing the psw. non-maskable interrupt requests and exceptions are acknowledged regardless of this flag. when a maskable interrupt is acknowledged, the id flag is automatically set to 1 by hardware. when interrupt servicing is completed, the fl ag is cleared by reti instruction execution. the interrupt request generated during the acknowledgment disabled period (id = 1) is acknowledged when the xxifn bit of xxicn is set to 1, and the id flag is reset to 0.
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 357 16.4 external interrupt request i nput pins (nmi, intp0 to intp2) 16.4.1 noise elimination (1) noise elimination for nmi pin the nmi pin includes a noise eliminator that operates using analog delay. t herefore, a signal input to the nmi pin is not detected as an edge unless it maintains its input level for a ce rtain period. the edge is detected only after a certain period has elapsed. the nmi pin can be used for releasing the stop mode. in the stop mode, noise elimination using the system clock is not performed because t he internal system clock is stopped. (2) noise elimination for intp0 to intp2 pins the intp0 to intp2 pins include a noise eliminator t hat operates using analog dela y. therefore, a signal input to each pin is not detected as an edge unless it ma intains its input level for a certain period. the edge is detected only after a certain period has elapsed. the intp0 to intp2 pins can be used for releasing th e stop mode. in the stop mode, noise elimination using the system clock is not performed bec ause the internal system clock is stopped. 16.4.2 edge detection the valid edges of the nmi and intp0 to intp2 pins can be selected from the following four types for each pin. ? rising edge ? falling edge ? both edges ? no edge detection after reset, the edge detection for the nmi and intp0 to in tp2 pins is set to ?no edge detection?. therefore, interrupt requests cannot be acknowledged (the nmi pin func tions as a normal port) unless a valid edge is specified by the intf0 and intr0 registers. when using port 0 as an output port, set the nmi and intp0 to intp2 pin valid edge to ?no edge detection?.
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 358 (1) external interrupt rising edge specification register 0 (intr0), external interrupt falling edge specification register 0 (intf0) intr0 and intf0 are 8-bit registers that specify detection of the rising and falling edges of the nmi and intp0 to intp2 pins. these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the extern al interrupt function (alternate function) to the port function, an edge may be detected. there fore, clear the intf0n and intr0n bits to 0, and then set the port mode. 0 intr0 0 0 0 intr03 intp2 intp1 intp0 nmi intr02 intr01 intr00 < > < > < > < > after reset: 00h r/w address: intr0 fffffc20h, intf0 fffffc00h 0 intf0 0 0 0 intf03 intf02 intf01 intf00 < > < > < > < > intp2 intp1 intp0 nmi remark for how to specify a valid edge, see table 16-3 . table 16-3. valid edge specification intf0n intr0n valid edge specification (n = 0 to 3) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 0: control of nmi pin n = 1 to 3: control of intp0 to intp2 pins
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 359 16.5 software exception a software exception is generated when the cpu ex ecutes the trap instruction, and can always be acknowledged. 16.5.1 operation if a software exception occurs, the cpu performs the fo llowing processing, and transfers control to the handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the psw.ep and psw.id bits (1). <5> sets the handler address (00000040h or 00000050h ) corresponding to the software exception to the pc, and transfers control. figure 16-8 illustrates the proce ssing of a software exception. figure 16-8. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (the vector is a value from 00h to 1fh.) the handler address is determined by the trap instruction? s operand (vector). if the vector is 00h to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h.
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 360 16.5.2 restore recovery from software exception processing is carried out by the reti instruction. by executing the reti instruction, t he cpu carries out the following processi ng and shifts control to the restored pc?s address. <1> loads the restored pc and psw from ei pc and eipsw because the psw.ep bit is 1. <2> transfers control to the address of the restored pc and psw. figure 16-9 illustrates the proce ssing of the reti instruction. figure 16-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the software exception processing, in order to r estore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before th e reti instruction. remark the solid line shows the cpu processing flow.
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 361 16.5.3 exception status flag (ep) the ep flag is bit 6 of the psw, and is a status flag used to indicate that exception processing is in progress. it is set when an exception occurs. 0 np ep id sat cy ov s z psw exception processing not in progress. exception processing in progress. ep 0 1 exception processing status after reset: 00000020h
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 362 16.6 exception trap an exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. in the v850es/pm1, an illegal opcode exception (ilgop: illegal opcode trap) is considered as an exception trap. 16.6.1 illegal opcode definition the illegal instruction has an opcode (bits 10 to 5) of 111111b, a sub-opcode (bits 26 to 23) of 0111b to 1111b, and a sub-opcode (bit 16) of 0b. an exception trap is generated when an instruction applicable to this illegal instruction is executed. 15 16 23 22 xxxxxx0 x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to x: arbitrary caution since it is possible to assign this instruction to an illegal opcode in the future, it is recommended that it not be used. (1) operation if an exception trap occurs, the cpu performs the followi ng processing, and transfers control to the handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits (1). <4> sets the handler address (00000060h) correspondi ng to the exception trap to the pc, and transfers control. figure 16-10 illustrates the processing of the exception trap.
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 363 figure 16-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore recovery from an exception trap is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following proce ssing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. figure 16-11 illustrates the restore processing from an exception trap. figure 16-11. restore processing from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 364 16.6.2 debug trap the debug trap is an exception that can be acknowle dged every time and is generated by execution of the dbtrap instruction. when the debug trap is generated, the cpu performs the following processing. (1) operation <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep and psw.id bits of the (1). <4> sets the handler address (00000060h) corresponding to the debug trap to the pc and transfers control. figure 16-12 illustrates the processing of the debug trap. figure 16-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 365 (2) restore recovery from a debug trap is carried out by the dbre t instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. figure 16-13 illustrates the restor e processing from a debug trap. figure 16-13. restore processing from debug trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 366 16.7 interrupt acknowledge time of cpu the interrupt response time from generation of an interrupt request to the start of interrupt servicing is illustrated below. figure 16-14. pipeline operation at inte rrupt request acknowledgment (outline) internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (start instruction of interrupt service routine) interrupt request if id ex df wb ifx idx 4 system clocks if if id ex int1 int2 int3 int4 remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt acknowledge time (internal system clock) internal interrupt external interrupt condition minimum 4 4 + analog delay time maximum 6 6 + analog delay time the following cases are exceptions. ? in idle/software stop/sub-idle/sub-software stop mode ? external bus access ? two or more interrupt request non-sample instructions are executed in succession ? access to peripheral i/o register
chapter 16 interrupt/exception processing function user?s manual u16237ej3v0ud 367 16.8 periods in which interrupts are not acknowledged by cpu an interrupt is acknowledged by the cpu while an instru ction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sample instructi on and the next instruction (int errupt is held pending). the interrupt request non-sample instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? the store instruction for the command register (prcmd) ? the load, store, set1, not1, and clr1 instructions for the following interrupt-related registers. interrupt control register (xxicn), interr upt mask registers 0 and 1 (imr0 and imr1)
user?s manual u16237ej3v0ud 368 chapter 17 standby function 17.1 overview the power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. the available stan dby modes are listed in table 17-1. table 17-1. standby modes mode functional outline halt mode mode to stop only the operating clock of the cpu idle mode mode to stop all the operations of the internal circuit except the oscillator and rtc note software stop mode mode to stop all the operations of the internal circuit except the subclock oscillator and rtc note subclock operation mode mode to use the subclock as the internal system clock sub-idle mode mode to stop all the operations of the internal circuit, except the oscillator and rtc note , in the subclock operation mode sub-software stop mode mode to stop rtc and all the internal operations of the v850es/pm1, including the oscillator, in the subclock operation mode note when rtc operation is enabled
chapter 17 standby function user?s manual u16237ej3v0ud 369 figure 17-1. status transition normal operation mode (operation with main clock) wait for stabilization of oscillation wait for stabilization of oscillation wait for stabilization of oscillation end of oscillation stabilization time count end of oscillation stabilization time count end of oscillation stabilization time count setting of halt mode interrupt request note 1 setting of stop mode idle mode halt mode software stop mode reset pin input interrupt request note 2 setting of idle mode interrupt request note 3 reset pin input reset pin input notes 1. non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp2 pin input), or unmasked internal interrupt request from peripheral functions operable in idle mode. 2. non-maskable interrupt reques t (nmi pin input) or unmasked maskable interrupt request. 3. non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp2 pin input), or unmasked internal interrupt request from peripheral functions operable in software stop mode.
chapter 17 standby function user?s manual u16237ej3v0ud 370 figure 17-2. status transition (during subclock operation) normal operation mode (operation with main clock) wait for stabilization of oscillation (main) sub-idle mode subclock operation mode sub-software stop mode wait for stabilization of oscillation (main) wait for stabilization of oscillation (sub) end of oscillation stabilization time count end of oscillation stabilization time count end of oscillation stabilization time count reset pin input setting of main clock operation setting of subclock operation setting of sub- idle mode setting of sub-software stop mode interrupt request note 2 interrupt request note 1 reset pin input reset pin input notes 1. non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp2 pin input), or unmasked internal interrupt r equest from peripheral functions operable in sub- software stop mode. 2. non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp2 pin input), or unmasked internal interrupt r equest from peripheral functions operable in sub- idle mode.
chapter 17 standby function user?s manual u16237ej3v0ud 371 17.2 registers (1) power save control register (psc) psc is an 8-bit register that controls the standby function. the stp bit of this register is used to specify the idle/software stop mode. the psc r egister is a special register (see 3.4.8 special registers ). data can be written to this register only in a specific sequence so that its contents are not rewri tten by mistake due to a program hang-up. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 psc 0 nmi0m intm 0 0 stp note < > < > < > 0 release enabled release disabled nmi0m 0 1 standby mode release control by nmi pin input release enabled release disabled intm 0 1 standby mode release control by maskable interrupt request normal operation mode standby mode note stp note 0 1 standby mode setting after reset: 00h r/w address: fffff1feh note when setting software stop mode, set the psmr.psm bit and then set the stp bit to 1. (2) power save mode register (psmr) psmr is an 8-bit register that contro ls the operation status and clock op eration in the power save mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 idle mode software stop mode psm 0 1 specifies operation in software standby mode psmr 0 0 0 0 0 0 psm after reset: 00h r/w address: fffff820h < > cautions 1. be sure to clear bits 1 to 7 of the psmr register to ?0?. 2. the psm bit is valid only when the psc.stp bit is set to 1.
chapter 17 standby function user?s manual u16237ej3v0ud 372 (3) oscillation stabilization time select register (osts) the osts register controls the wait time until the os cillation stabilizes after the software stop/sub-software stop mode is released. this register is set by an 8-bit memory manipulation instruction. reset sets this register to 04h. 0 osts 0 0 0 0 osts2 osts1 osts0 2 14 /f x , 2 14 /f xt 2 16 /f x , 2 16 /f xt 2 17 /f x , 2 17 /f xt 2 18 /f x , 2 18 /f xt 2 19 /f x , 2 19 /f xt 2 20 /f x , 2 20 /f xt 2 21 /f x , 2 21 /f xt 2 22 /f x , 2 22 /f xt osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 10 mhz 32.768 khz 500 ms 2.0 s 4.0 s 8.0 s 16 s 32 s 64 s 128 s 20 mhz 0.819 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 1.638 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms f x f xt after reset: 04h r/w address: fffff6c0h cautions 1. the wait time follow ing release of the software stop m ode does not include the time until the clock oscillation starts (?a? in the figure below) following release of the software stop mode, regardless of whether the stop mode is released through reset input or the occurrence of an interrupt request signal. a stop mode release voltage waveform of x1, xt1 pins v ss 2. be sure to clear bits 3 to 7 to ?0?. 3. the oscillation stabilization ti me following reset release is 2 19 /f x (because the initial value of the osts register = 04h). remark f x = main clock oscillation frequency
chapter 17 standby function user?s manual u16237ej3v0ud 373 17.3 halt mode 17.3.1 setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. in the halt mode, the clock oscillator continues operating. only clock supply to the cpu is stopped; clock supply to the other on-chip peripheral functions continues. as a result, program execution is stopped, and the inte rnal ram retains the contents before the halt mode was set. the on-chip peripheral functions that are independent of instruction processing by the cpu continue operating. table 17-3 shows the operation status in the halt mode. the average power consumpti on of the system can be reduced by using the halt mode in combination with the normal operation mode for intermittent operation. cautions 1. insert five or more nop in structions after the halt instruction. 2. if the halt instruction is executed with an interrupt request signal held pending, the system shifts to the halt mode, but the halt mode is immediately released by the pending interrupt request. 17.3.2 releasing halt mode the halt mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request, and reset pin input. after the halt mode has been released, the normal operation mode is restored. (1) releasing halt mode by non-m askable interrupt request or unmasked maskable interrupt request the halt mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt request. if t he halt mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the halt mode is rel eased, and that interrupt request is not acknowledged. the interrupt request itself is retained. (b) if an interrupt request with a priority higher than th at of the interrupt request currently being serviced is issued (including a non-maskable interru pt request), the halt mode is re leased and that interrupt request is acknowledged. table 17-2. operation after releas ing halt mode by interrupt request release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request execution branches to the handler address maskable interrupt request execution branches to the handler address or the next instruction is executed the next instruction is executed (2) releasing halt mode by reset pin input the same operation as the normal reset operation is performed.
chapter 17 standby function user?s manual u16237ej3v0ud 374 table 17-3. operation status in halt mode setting of halt mode operation status item when subclock is not used when subclock is used main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled cpu stops operation interrupt controller operable rom correction stops operation 16-bit timer/event counters (tm00 to tm03, tm10, tm11) operable 8-bit timer/event counters (tm20, tm21) operable real-time counter ? operable watchdog timer operable note csi0, csi1 operable serial interface uart0, uart1 operable a/d converter operable pwm (pwm0 to pwm3) operable external bus interface see 2.2 pin status . port function retains status before halt mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the halt mode was set. note take care to prevent an overflow from occurring because the watchdog timer operates in the halt mode.
chapter 17 standby function user?s manual u16237ej3v0ud 375 17.4 idle mode 17.4.1 setting and operation status the idle mode is set by clearing the psmr.psm bit to 0 and setting the psc.stp bit to 1 in the normal operation mode. in the idle mode, the clock oscillator continues operation but clock supply to the cpu and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle mode was set are retained. the cpu and other on-chip peripheral functions st op operating. however, the on- chip peripheral functions that can operate with the subclock or an external clock continue operating. table 17-5 shows the operation status in the idle mode. the idle mode can reduce the power consumption more t han the halt mode because it stops the operation of the on-chip peripheral functions. the main clock osc illator does not stop, so t he normal operation mode can be restored without waiting for the oscillation stabilization ti me after the idle mode has been released, in the same manner as when the halt mode is released. caution insert five or more nop instru ctions after the instruction that st ores data in the psc register to set the idle mode. 17.4.2 releasing idle mode the idle mode is released by a non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp2 pin input), unm asked internal interrupt request from the peripheral functions operable in the idle mode, or reset input. after the idle mode has been released, th e normal operation mode is restored. (1) releasing idle mode by non-m askable interrupt request or unm asked maskable interrupt request the idle mode is released by a non-maskable interr upt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt request. if t he idle mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is processed as follows. (a) if an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the idle mode is rel eased, and that interrupt request is not acknowledged. the interrupt request itself is retained. (b) if an interrupt request with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the idle mode is released and that interrupt request is acknowledged. table 17-4. operation after releasi ng idle mode by interrupt request release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request execution branches to the handler address maskable interrupt request execution branches to the handler address or the next instruction is executed the next instruction is executed (2) releasing idle mode by reset pin input the same operation as the normal reset operation is performed.
chapter 17 standby function user?s manual u16237ej3v0ud 376 table 17-5. operation status in idle mode setting of idle mode operation status item when subclock is not used when subclock is used main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled cpu stops operation interrupt controller stops operation (mode releasing request can be acknowledged) rom correction stops operation 16-bit timer/event counters (tm00 to tm03, tm10, tm11) stops operation 8-bit timer/event counters (tm20, tm21) stops operation real-time counter ? operable watchdog timer stops operation csi0, csi1 operable when sckn input clock is selected as operation clock (n = 0, 1) serial interface uart0, uart1 stops operation a/d converter stops operation pwm (pwm0 to pwm3) stops operation external bus interface see 2.2 pin status . port function retains status before idle mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle mode was set.
chapter 17 standby function user?s manual u16237ej3v0ud 377 17.5 software stop mode 17.5.1 setting and operation status the software stop mode is set when the psmr.psm bit is set to 1 and the stp bit of the psc register is set to 1 in the normal operation mode. in the software stop mode, the subclock oscillator conti nues operating but the main clock oscillator stops. clock supply to the cpu and the on-chip pe ripheral functions is stopped. as a result, program execution is st opped, and the conten ts of the internal ram before the software stop mode was set are retained. the on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator or an external clock continue operating. table 17-7 shows the operation stat us in the software stop mode. because the software stop stops operatio n of the main clock oscillator, it reduces the current consumption to a level lower than the idle mode. if the subclock oscillator and external clock are not used, the power consumption can be minimized with only leakage current flowing. caution insert five or more nop instru ctions after the instruction that st ores data in the psc register to set the software stop mode. 17.5.2 releasing soft ware stop mode the software stop mode is released by a non-maskable in terrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp2 pin input), unmasked in ternal interrupt request from the peripheral functions operable in the software stop mode, or reset pin input. after the software stop mode has been released, the no rmal operation mode is restored after the oscillation stabilization time has been secured. (1) releasing software stop mode by non-maskable interrupt reque st or unmasked maskable interrupt request the software stop mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt reques t. if the software stop mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the software stop mode is released, and that interrupt request is not acknowledged. the interrupt request itself is retained. (b) if an interrupt request with a priority higher than th at of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the software stop mode is released and that interrupt request is acknowledged. table 17-6. operation after releasing so ftware stop mode by interrupt request release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request execution branches to the handler address maskable interrupt request execution branches to the handler address or the next instruction is executed the next instruction is executed
chapter 17 standby function user?s manual u16237ej3v0ud 378 (2) releasing software stop mode by reset pin input the same operation as the normal reset operation is performed. table 17-7. operation status in software stop mode operation status setting of software stop mode item when subclock is not used when subclock is used main clock oscillator stops operation subclock oscillator ? oscillation enabled cpu stops operation interrupt controller stops operation (mode releasing request can be acknowledged) rom correction stops operation 16-bit timer/event counters (tm00 to tm03, tm10, tm11) stops operation 8-bit timer/event counters (tm20, tm21) stops operation real-time counter ? operable watchdog timer stops operation csi0, csi1 operable when sckn input clock is selected as operation clock (n = 0, 1) serial interface uart0, uart1 stops operation a/d converter stops operation pwm (pwm0 to pwm3) stops operation external bus interface see 2.2 pin status . port function retains status before software stop mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the software stop mode was set.
chapter 17 standby function user?s manual u16237ej3v0ud 379 17.6 securing oscillation stabilization time when the software stop mode or sub-so ftware stop mode is released, only the oscillation stabilization time set by the osts register elapses. if the software stop m ode has been released by reset pin input, however, the reset value of the osts register, 2 19 /f x elapses. figure 17-3 shows the operation performed when the softw are stop mode is released by an interrupt request. figure 17-3. oscillation stabilization time oscillated waveform main clock oscillator stops oscillation stabilization time count main clock software stop mode status interrupt request caution for details of the osts register, see 17.2 (3) oscillation stabilizat ion time select register (osts).
chapter 17 standby function user?s manual u16237ej3v0ud 380 17.7 subclock operation mode 17.7.1 setting and operation status the subclock operation mode is set when the pcc.ck3 bit is set to 1 in the normal operation mode. when the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. when the pcc.mck bit is set to 1, the operation of the main clock oscillator is stopped. as a result, the system operates only with the subclock. however, watchdog time r stops counting when subclock operation is started (pcc.cls bit = 1). (watchdog timer retains the va lue before the subclock operation mode was set.) in the subclock operation mode, the power consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system clock. in addition, the power consumption can be further reduced to the level of the software stop mode by stopping the operation of the main system clock oscillator. table 17-8 shows the operation stat us in subclock operation mode. cautions 1. when manipulating the ck3 bit, do not change the set values of the pcc.ck1 and pcc.ck0 bits (using a bit manipulation instruction to manipulate the bi t is recommended). for details of the pcc register, see 6.3 (1) pr ocessor clock control register (pcc). 2. to select the subclock operation and stop the main clock, stop the operations of tm00 to tm03, tm10, tm11, tm20, tm21, uart0, uart1, and pwm0 to pwm3. 3. the watchdog timer stops during the subclock operation. do not write anything to the wdtm register. 17.7.2 releasing subc lock operation mode the subclock operation mode is released by reset pin i nput when the ck3 bit is cleared to 0. if the main clock is stopped (mck bit = 1), clear the mck bit to 0, secure the osc illation stabilization time of the main clock by software, and clear the ck3 bit to 0. the normal operation mode is restored when the subclock operation mode is released. caution when manipulating the ck3 bit, do not chan ge the set values of the ck1 and ck0 bits (using a bit manipulation instruction to ma nipulate the bit is recommended). for details of the pcc register, see 6.3 (1 ) processor clock control register (pcc).
chapter 17 standby function user?s manual u16237ej3v0ud 381 17.7.3 registers to which access is di sabled in subclock operation mode while the cpu is operating on the subclock and a clock is not input to x1 or when the main oscillator is stopped, do not access the following registers in which a wait is generat ed using an access method that causes a wait. if a wait is generated, only a reset can release the wait. for details, see 3.4.8 (2) . peripheral function register name access method watchdog timer (wdt) wdtm write tm10, tm11 read read (in capture mode) cc100, cc101, cc110, cc111 write (in compare mode) write 16-bit timer/event counters (tm10, tm11) tmc100, tmc110 read modify write pwm pwmb0 to pwmb3 write table 17-8. operation status in subclock operation mode operation status setting of subclock operation mode item when main clock is oscillating when main clock is stopped subclock oscillator oscillation enabled cpu operable interrupt controller operable rom correction operable 16-bit timer/event counters (tm00 to tm03, tm10, tm11) operable stops operation 8-bit timer/event counters (tm20, tm21) operable stops operation real-time counter operable watchdog timer stops operation csi0, csi1 operable operable when sckn input clock is selected as operation clock (n = 0, 1) note serial interface uart0, uart1 operable stops operation a/d converter operable stops operation pwm (pwm0 to pwm3) operable stops operation external bus interface operable note port function settable internal data settable note operation when v dd 2.7 v is not guaranteed.
chapter 17 standby function user?s manual u16237ej3v0ud 382 17.8 sub-idle mode 17.8.1 setting and operation status the sub-idle mode is set when the psmr.psm bit is cleared to 0 and the psc.stp bit is set to 1 in the subclock operation mode. in this mode, the clock oscillator c ontinues operation but clock supply to the cpu and the other on-chip peripheral functions is stopped. as a result, program execution is stopped and the contents of the internal ram before the sub-idle mode was set are retained. the cpu and the other on-chip peripheral functions are stopped. however, the on-chip peripheral functions that can operate with the subclock or an extern al clock continue operating. because the sub-idle mode stops operat ion of the cpu and other on-chip per ipheral functions, it can reduce the power consumption more than the subclo ck operation mode. if the sub-idle mode is set after the main clock has been stopped, the current consumption can be reduced to a level as low as that in the software stop mode. table 17-10 shows the operation status in the sub-idle mode. caution insert five or more nop inst ructions after the instruction that stores data in the psc register to set the sub-idle mode. 17.8.2 releasing sub-idle mode the sub-idle mode is released by a non-maskable interrup t request (nmi pin input), unmasked external interrupt request (intp0 to intp2 pin input), unm asked internal interrupt request from the peripheral functions operable in the sub-idle mode, or reset pin input. when the sub-idle mode is released by an interrupt reques t, the subclock operation mode is set. if it is released by reset pin input, the normal operation mode is restored. (1) releasing sub-idle m ode by non-maskable interrupt request or unmasked mas kable interrupt request the sub-idle mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt reques t. if the sub-idle mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the sub-idle mode is released, and that interrupt request is not acknowledged. the interrupt request itself is retained. (b) if an interrupt request with a priority higher than th at of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the sub-idle mode is released and that interrupt request is acknowledged. table 17-9. operation after releasing sub-idle mode by interrupt request release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request execution branches to the handler address maskable interrupt request execution branches to the handler address or the next instruction is executed the next instruction is executed
chapter 17 standby function user?s manual u16237ej3v0ud 383 (2) releasing sub-idle m ode by reset pin input the same operation as the normal reset operation is performed. table 17-10. operation status in sub-idle mode setting of sub-idle mode operation status item when main clock is oscillating when main clock is stopped subclock oscillator oscillation enabled cpu stops operation interrupt controller stops operation (mode releasing request can be acknowledged) rom correction stops operation 16-bit timer/event counters (tm00 to tm03, tm10, tm11) stops operation 8-bit timer/event counters (tm20, tm21) stops operation real-time counter operable watchdog timer stops operation csi0, csi1 operable when sckn input clock is selected as operation clock (n = 0, 1) serial interface uart0, uart1 stops operation a/d converter stops operation pwm (pwm0 to pwm3) stops operation external bus interface see 2.2 pin status . port function retains status before sub-idle mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the sub-idle mode was set.
chapter 17 standby function user?s manual u16237ej3v0ud 384 17.9 sub-software stop mode 17.9.1 setting and operation status the sub-software stop mode is set when the psmr.psm bit is set to 1 and the psc.stp bit is set to 1 in the subclock operation mode. in the sub-software stop mode, the subclock oscillator and main clock oscillator are stopped. therefore, clock supply to the cpu and other on-chip peripheral functions is stopped. table 17-12 shows the operation status in the sub-software stop mode. caution insert five or more nop inst ructions after the instruction that stores data in the psc register to set the sub-software stop mode. 17.9.2 releasing sub-software stop mode the sub-software stop mode is released by a non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp2 pin input), unmasked in ternal interrupt request from the peripheral functions operable in the sub-software stop mode, or reset pin input. when the sub-software stop mode is released by an interrupt r equest, the subclock operation mode is set. if it is released by reset pin input, the normal operation mode is restored. (1) releasing sub-software stop mode by non-maskable interrupt request or unmasked maskable interrupt request the sub-software stop mode is released by a non -maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interr upt request. if the sub-software stop mode is set in an interrupt servicing routine, however, an interrupt r equest that is issued later is serviced as follows. (a) if an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the sub-software stop mode is released, and that interrupt request is not acknowledged. the interrupt request itself is retained. (b) if an interrupt request with a priority higher than th at of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the sub-software stop mode is released and that interrupt request is acknowledged. table 17-11. operation after releasing sub- software stop mode by interrupt request release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request execution branches to the handler address maskable interrupt request execution branches to the handler address or the next instruction is executed the next instruction is executed (2) releasing sub-idle m ode by reset pin input the same operation as the normal reset operation is performed.
chapter 17 standby function user?s manual u16237ej3v0ud 385 table 17-12. operation status in sub-software stop mode item operation status main clock oscillator stops operation subclock oscillator stops operation cpu stops operation interrupt controller stops operation (mode releasing request can be acknowledged) rom correction stops operation 16-bit timer/event counters (tm00 to tm03, tm10, tm11) stops operation 8-bit timer/event counters (tm20, tm21) stops operation real-time counter stops operation watchdog timer stops operation csi0, csi1 operable when sckn input clock is selected as operation clock (n = 0, 1) serial interface uart0, uart1 stops operation a/d converter stops operation pwm (pwm0 to pwm3) stops operation external bus interface power supply stopped port function retains status before sub-software stop mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the sub-software stop mode was set.
user?s manual u16237ej3v0ud 386 chapter 18 reset function 18.1 overview the following reset functions are available. ? reset function by reset pin input ? reset function by wdt overflow (wdtres) if the reset pin goes high, the reset stat us is released, and the cp u starts executing the program. initialize the contents of each register in the program as necessary. the reset pin has a noise e liminator that operat es by analog delay to prevent malfunction caused by noise. a flag (wresf) that detects occurrence of reset because of overflow of the wdt is also provided. this flag identifies whether reset is effected by reset pin input or overflow of the wdt during processing after the reset has been released. 18.2 configuration figure 18-1. reset block diagram reset count clock analog delay circuit reset controller watchdog timer wdtres issued due to overflow reset signal to cpu reset signal to cg reset signal to other peripheral macros
chapter 18 reset function user?s manual u16237ej3v0ud 387 18.3 register (1) wdt reset status register (wdres) wdres is an 8-bit register that indicates the status of wdtres, and can be read or written by using an 8-bit or 1-bit manipulation instruction. to write the wdres register, a spec ific sequence using prcdm as a command register is required. if the register is written in an illegal sequ ence, writing is invalid and the protect error flag (the sys.prerr bit) is set to 1, and nothing is written to the register. this register is cleared to 00h by reset pin input, and is set to 01h when the wdtres signal is generated. wdres wdtres did not occur wdtres occurred setting (1) condition: reset by overflow of watchdog timer (wdt) clearing (0) condition: writing ?0? by instruction or reset pin input. only ?0? can be written to the wresf bit. wresf 0 1 wdtres detection flag after reset: undefined r/w address: fffff82ah 0 0 0 0 0 0 0 wresf <0> 1 2 3 4 5 6 7 caution write ?0? to the wresf bit after confirming (r eading) that the wresf bit is 1 to avoid a conflict with setting the flag. remark the wresf bit can be read or written, but it can onl y be cleared by writing ?0?. ?1? cannot be written to it.
chapter 18 reset function user?s manual u16237ej3v0ud 388 18.4 operation the system is reset, initializing each hardware unit, when a low level is input to the reset pin or by wdt overflow (wdtres signal) note . if the reset pin goes high or if the wdtres si gnal is received, the rese t status is released. if the reset status is released by reset pin input, the o scillation stabilization time elapses (reset value of osts register: 2 19 /f x ) and then the cpu starts program execution. if the reset status is released by the wdtres signal, t he oscillation stabilization time is not inserted because the main system clock oscill ator does not stop. note reset by wdt overflow (wdtres signal) is valid only when the wdtm.wdtm4 and wdtm.wdtm3 bits are set to ?11? (see 11.3 (2) ). table 18-1. hardware status on reset pin input item during reset after reset main clock oscillator (f x ) oscillation stops (f x = 0 level). oscillation starts subclock oscillator (f xt ) oscillation can continue without effect from reset note 1 . peripheral clock (f x to f x /1024), internal system clock (f clk ), cpu clock (f cpu ) operation stops operation starts. however, operation stops during oscillation stabilization time count. wdt clock (f xw ) operation stops operation starts note 2 internal ram undefined if power-on reset occurs or writing data to ram and reset conflict (data loss). otherwise, retains values i mmediately before reset input. i/o lines (ports) high impedance on-chip peripheral i/o registers initialized to specified status real-time counter operation can be started note 3 other on-chip peripheral functions oper ation stops operation can be started notes 1. the on-chip feedback resistor is ?connected? by default (see 6.3 (1) processor clock control register (pcc) ). 2. the wdt clock is in the initia l status (interval timer mode). 3. if the subclock is supplied, therefore, the real-tim e counter performs a count operation on the subclock after reset.
chapter 18 reset function user?s manual u16237ej3v0ud 389 table 18-2. hardware status on occurrence of wdtres item during reset after reset main clock oscillator (f x ) oscillation continues note 1 subclock oscillator (f xt ) oscillation can continue without effect from reset note 1 . peripheral clock (f x to f x /1024), internal system clock (f clk ), cpu clock (f cpu ) operation stops operation starts wdt clock (f xw ) operation continues internal ram undefined if writing data to ram and reset conflict (data loss). otherwise, retains values i mmediately before reset input. i/o lines (ports) high impedance on-chip peripheral i/o registers initialized to specified status real-time counter operation continues note 2 other on-chip peripheral functions oper ation stops operation can be started notes 1. the on-chip feedback resistor is ?connected? by default (see 6.3 (1) processor clock control register (pcc) ). 2. reset sets the internal peripheral i/o register of the real-time counter so t hat its count operation by subclock (f xt ) is enabled. if the subclock is supplied, t herefore, the real-time counter performs a count operation on the subclock after reset. figure 18-2. hardware status on reset input oscillation stabilization time count initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal analog delay (eliminated as noise) analog delay analog delay (eliminated as noise) reset f x f clk analog delay
chapter 18 reset function user?s manual u16237ej3v0ud 390 figure 18-3. operation on power application oscillation stabilization time count must be 2 s or longer. initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal reset f x v dd f clk analog delay caution turn on v dd (power supply for internal circuits) and ev dd (power supply for external circuits) in that order. if ev dd is turned on first, the status of each pin is undefined until the reset function operates. consequently, input and output of a port may conflict.
user?s manual u16237ej3v0ud 391 chapter 19 rom correction function 19.1 overview the rom correction function is used to replace part of the program in the mask rom with the program of an external memory or the internal ram. by using this function, instruction bugs found in the mask rom can be corrected. up to four addresses can be specified for correction. figure 19-1. block diagram of rom correction instruction address bus block replaced by dbtrap instruction instruction data bus rom dbtrap instruction generation block correction address register n (coradn) correction control register (corenn bit) comparator remark n = 0 to 3
chapter 19 rom correction function user?s manual u16237ej3v0ud 392 19.2 registers 19.2.1 correction address register s 0 to 3 (corad0 to corad3) corad0 to corad3 are used to set the fi rst address of the program to be corrected. the program can be corrected at up to four places because four coradn r egisters are provided (n = 0 to 3). the coradn register can only be r ead or written in 32-bit units. if the higher 16 bits of the coradn register are used as the coradnh regi ster, and the lower 16 bits as the coradnl register, these registers can be read or written in 16-bit units. set correction addresses within the range of 0000000h to 003fffeh. fix bits 0 and 18 to 31 to 0. reset sets these registers to 00000000h. correction address fixed to 0 0 coradn (n = 0 to 3) after reset: 00000000h r/w address: refer to table 19-1 . 1817 table 19-1. address of coradn fffff840h corad0 fffff848h corad2 fffff840h corad0l fffff848h corad2l fffff842h corad0h fffff84ah corad2h fffff844h corad1 fffff84ch corad3 fffff844h corad1l fffff84ch corad3l fffff846h corad1h fffff84eh corad3h
chapter 19 rom correction function user?s manual u16237ej3v0ud 393 19.2.2 correction control register (corcn) corcn is a register that disables or enables the corre ction operation at the addre ss specified by the coradn register (n = 0 to 3). each channel can be enabled or disabled by this register. this register is set by using an 8-bit or 1-bit memory manipulation instruction. reset sets this register to 00h. 0 disabled enabled corenn 0 1 enables/disables correction operation corcn 0 0 0 coren3 coren2 coren1 coren0 after reset: 00h r/w address: fffff880h <3> <2> <1> <0> remark n = 0 to 3 table 19-2. correspondence between corcn register bits and coradn registers corcn register bit corresponding coradn register coren3 corad3 coren2 corad2 coren1 corad1 coren0 corad0 19.3 rom correction operation and program flow <1> if the address to be corrected and the fetch address of the internal rom match, the fetch code is replaced by the dbtrap instruction. <2> when the dbtrap instruction is execut ed, execution branches to address 00000060h. <3> software processing after branching causes the resu lt of rom correction to be judged (the fetch address and rom correction operation are confirmed) and exec ution to branch to the correction software. <4> after the correction software has been executed, the re turn address is set, and return processing is started by the dbret instruction. cautions 1. the software that pe rforms <3> and <4> must be ex ecuted in the internal rom/ram. 2. when setting an address to be corrected to the coradn register, clear the higher bits to 0 in accordance with the capacity of the internal rom. 3. the rom correction function cannot be used to correct the data of the internal rom. it can only be used to correct instructi on codes. if rom correction is u sed to correct data, that data is replaced with the dbtrap instruction code.
chapter 19 rom correction function user?s manual u16237ej3v0ud 394 figure 19-2. rom correction operation and program flow reset & start fetch address = coradn? coradn = dbpc-2? corenn bit = 1? initialize microcontroller set coradn register change fetch code to dbtrap instruction branch to rom correction judgment address branch to correction code address of corresponding channel n execute fetch code read data for setting rom correction from external memory execute dbtrap instruction jump to address 00000060h execute correction code execute dbret instruction write return address to dbpc. write value of psw to dbpsw as necessary. set corcn register yes yes yes no no remarks 1. : processing by user program (software) 2. n = 0 to 3 : processing by rom correction (hardware) load program for judgment of rom correction and correction codes execute fetch code ilgop processing no
user?s manual u16237ej3v0ud 395 chapter 20 electrical specifications absolute maximum ratings (t a = 25c, v ss = 0 v) parameter symbol conditions ratings unit v dd ? 0.5 to +4.6 v av dd ? 0.5 to +4.6 v ev dd ? 0.5 to +4.6 v av ss ? 0.5 to +0.5 v supply voltage ev ss ? 0.5 to +0.5 v input voltage v i pins other than x1, x2 ? 0.5 to ev dd + 0.5 note v clock input voltage v k x1, x2, v dd = 2.7 to 3.6 v ? 0.5 to v dd + 0.5 note v analog input voltage v ian ? 0.5 to av dd + 0.5 note v analog reference voltage av ref av refin ? 0.5 to av dd + 0.5 note v per pin 4 ma total for p0, p4, and pcs 35 ma total for p1 and p3 35 ma total for p2 and p9 35 ma output current, low i ol total for pcm, pct, pdl, and pdh 35 ma per pin ? 4 ma total for p0, p4, and pcs ? 35 ma total for p1 and p3 ? 35 ma total for p2 and p9 ? 35 ma output current, high i oh total for pcm, pct, pdl, and pdh ? 35 ma output voltage v o v dd = 2.7 to 3.6 v ? 0.5 to v dd + 0.5 note v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c note be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. cautions 1. do not directly connect the output (or i/ o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins , however, can be directly connected to each other. direct connection of the output pins betw een an ic product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. that is, the absolute maximu m ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolu te maximum ratings are not exceeded. the ratings and conditions indicated for dc ch aracteristics and ac characteristics represent the quality assurance range during normal operation.
chapter 20 electrical specifications user?s manual u16237ej3v0ud 396 capacitance (t a = 25c, v dd = av dd = ev dd = v ss = av ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 15 pf i/o capacitance c io 15 pf output capacitance c o f x = 1 mhz unmeasured pins returned to 0 v 15 pf operating conditions (t a = ? 40 to +85 c, v ss = av ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit @v dd = av dd = ev dd = 3.0 to 3.6 v, operation with main clock 0.25 note 1 20 note 2 mhz @v dd = av dd = ev dd = 2.7 to 3.6 v, operation with main clock 0.25 note 1 10 note 2 mhz internal system clock frequency f clk @v dd = av dd = ev dd = 2.2 to 3.6 v, operation with subclock 32.768 khz notes 1. main clock frequency: min. value of f xx condition is value of f xx divided by 8. 2. main clock frequency: max. value of f xx condition is undivided value of f xx .
chapter 20 electrical specifications user?s manual u16237ej3v0ud 397 recommended oscillator (1) main clock oscillator (t a = ? 40 to +85c) (a) connection of ceramic res onator or crystal resonator x1 x2 parameter symbol conditions min. typ. max. unit oscillation frequency f x (f xx ) v dd = 2.7 to 3.6 v 2 20 mhz upon reset release 2 19 /f x s oscillation stabilization time upon stop mode release note s note the value differs depending on the setting of the osts register. for details, see 17.2 (3) oscillation stabilizati on time select register (osts) . cautions 1. when using the main cl ock oscillator, wire as follows in th e area enclosed by the broken lines in the above figure to avoid an ad verse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor th e same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. ensure that the duty of the o scillation waveform is within 5.5:4.5. 3. for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
chapter 20 electrical specifications user?s manual u16237ej3v0ud 398 (2) external clock input (t a = ? 40 to +85 c) external clock high-speed cmos inverter x2 x1 parameter symbol conditions min. typ. max. unit oscillation frequency f x (f xx ) v dd = 2.7 to 3.6 v 2 20 mhz cautions 1. thoroughly evaluate matching of the pd703228 and the high-speed cmos inverter. 2. connect the high-speed cmos inverter as close as possible to the x1 and x2 pins.
chapter 20 electrical specifications user?s manual u16237ej3v0ud 399 (3) subclock oscillator (t a = ? 40 to +85c) (a) connection of crystal resonator xt1 xt2 parameter symbol conditions min. typ. max. unit oscillation frequency f xt v dd = 2.2 to 3.6 v 32 32.768 35 khz when reset is released 10 ms oscillation stabilization time when sub-stop mode is released note s note the value differs depending on the setting of the osts register. for details, see 17.2 (3) oscillation stabilizati on time select register (osts) . cautions 1. inputting an external clock to the subclock oscillator is prohibited. 2. when using the subclock oscillator, wire as fo llows in the area enclosed by the broken lines in the above figure to avoid an ad verse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor th e same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 3. ensure that the duty of the o scillation waveform is within 5.5:4.5. 4. thoroughly evaluate matching of the pd703228 and the resonator.
chapter 20 electrical specifications user?s manual u16237ej3v0ud 400 dc characteristics 1 (a) t a = ? 40 to +85c, v dd = av dd = ev dd = 2.7 to 3.6 v, v ss = av ss = ev ss = 0 v parameter symbol conditions min. typ. max. unit v ih1 note 1 0.7ev dd ev dd v v ih2 note 2 0.8ev dd ev dd v input voltage, high v ih3 x1, x2 0.8v dd v dd v v il1 note 1 ev ss 0.3ev dd v v il2 note 2 ev ss 0.2ev dd v input voltage, low v il3 x1, x2 v ss 0.2v dd v output voltage, high v oh1 i oh = ? 100 a ev dd ? 0.5 v output voltage, low v ol1 i ol = 100 a 0.4 v notes 1. p10 to p13, p20, p21, p31, p33, p41, p44, p 90 to p97, pcm0, pcm1, pc s0 to pcs2, pct0, pct1, pct4, pdh0 to pdh2, pdl0 to pdl15 (and their alternate-function pins) 2. reset, p00 to p03, p14, p30, p32, p34 to p36, p40, p42, p43, p45, p46, p98 to p915 (and their alternate-function pins) (b) t a = ? 40 to +85c, v dd = av dd = ev dd = 2.2 to 3.6 v, v ss = av ss = ev ss = 0 v parameter symbol conditions min. typ. max. unit v ih1 note 1 0.75ev dd ev dd v v ih2 note 2 0.85ev dd ev dd v input voltage, high v ih3 x1, x2 0.85v dd v dd v v il1 note 1 ev ss 0.25ev dd v v il2 note 2 ev ss 0.15ev dd v input voltage, low v il3 x1, x2 v ss 0.15v dd v output voltage, high v oh1 i oh = ? 100 a ev dd ? 0.5 v output voltage, low v ol1 i ol = 100 a 0.4 v notes 1. p10 to p13, p20, p21, p31, p33, p41, p44, p 90 to p97, pcm0, pcm1, pc s0 to pcs2, pct0, pct1, pct4, pdh0 to pdh2, pdl0 to pdl15 (and their alternate-function pins) 2. reset, p00 to p03, p14, p30, p32, p34 to p36, p40, p42, p43, p45, p46, p98 to p915 (and their alternate-function pins)
chapter 20 electrical specifications user?s manual u16237ej3v0ud 401 dc characteristics 2 (t a = ? 40 to +85c, v dd = av dd = ev dd = 2.2 to 3.6 v, v ss = av ss = ev ss = 0 v) parameter symbol conditions min. typ. note 1 max. unit pins other than x1, x2 5 a input leakage current, high i lih x1, x2 20 a pins other than x1, x2 ? 5 a input leakage current, low i lil x1, x2 ? 20 a pins other than x1, x2 5 a output leakage current, high i loh x1, x2 20 a pins other than x1, x2 ? 5 a output leakage current, low i lol x1, x2 ? 20 a i dd1 note 2 normal operation all peripheral functions operating f xx = f clk = 20 mhz 20 35 ma i dd2 note 2 halt mode all peripheral functions operating f xx = f clk = 20 mhz 16 25 ma i dd3 note 2 idle mode rtc operating f xx = 20 mhz 1.2 4.5 ma v dd = 3.3 v, subclock oscillation, rtc operating 10 57 a v dd = 3.3 v, t a = 50 c, subclock oscillation, rtc operating 27 a v dd = 3.3 v, subclock oscillation stopped (xt1 = v ss ) 1 37 a i dd4 note 3 stop mode, sub-stop mode v dd = 3.3 v, t a = 50 c, subclock oscillation stopped (xt1 = v ss ) 7 a v dd = 3.3 v, f xt = f clk = 32.768 khz, main clock oscillation stopped 42 97 a i dd5 note 3 subclock operation mode v dd = 3.3 v, t a = 50 c, f xt = f clk = 32.768 khz, main clock oscillation stopped 57 a v dd = 3.3 v, f xt = 32.768 khz, main clock oscillation stopped, rtc operating 10 57 a supply current i dd6 note 3 sub-idle mode v dd = 3.3 v, t a = 50 c, f xt = 32.768 khz, main clock oscillation stopped, rtc operating 27 a pull-up resistance r l v in = 0 v 10 30 100 k ? notes 1. the typical value of v dd is 3.3 v, and t a is 25 c, excluding the current that flows through the output buffer. 2. excluding the av dd supply current and the current that flows through the output buffer. the operating voltage range is v dd = av dd = ev dd = 2.7 to 3.6 v. 3. excluding the current that flows through the out put buffer. the operating voltage range is v dd = av dd = ev dd = 2.2 to 3.6 v.
chapter 20 electrical specifications user?s manual u16237ej3v0ud 402 data retention characteristics in stop mode (t a = ? 40 to +85c, v ss = av ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode, sub-stop mode 1.8 3.6 v v dd = 3.3 v note 2 , subclock oscillation, rtc operating 10 57 a v dd = 3.3 v note 2 , subclock oscillation, rtc operating, t a = 50 c 27 a v dd = 3.3 v note 2 , subclock oscillation stopped (xt1 = v ss ) 1 37 a data retention current i dddr note 1 stop mode, sub- stop mode v dd = 3.3 v note 2 , subclock oscillation stopped (xt1 = v ss ), t a = 50 c 7 a supply voltage rise time t rvd 200 s supply voltage fall time t fvd 200 s supply voltage hold time (from stop mode setting) t hvd 0 ms stop release signal input time t drel 0 ms data retention high-level input voltage v ihdr all input ports v ihn v dddr v data retention low-level input voltage v ildr all input ports 0 v iln v notes 1. excluding the current that fl ows through the output buffer. 2. v dd = v dddr remarks 1. n = 1 to 3 2. v ihn : high-level input voltage, v iln : low-level input voltage
chapter 20 electrical specifications user?s manual u16237ej3v0ud 403 v dd setting stop/sub-stop mode t hvd t fvd reset (input) nmi, intp0 to intp2 (input) (when stop or sub-stop mode is released at falling edge) nmi, intp0 to intp2 (input) (when stop or sub-stop mode is released at rising edge) t rvd t drel v dddr v ihdr v ildr v ihdr 2.2 v or 2.7 v or 3.0 v caution shifting to stop mode and restori ng from stop mode must be performed at v dd = 3.0 v min. (f clk = 20 mhz) or v dd = 2.7 v min. (f clk = 10 mhz). shifting to s ub-stop mode and restoring from sub-stop mode must be performed at v dd = 2.2 v min. (f clk = 32.768 khz).
chapter 20 electrical specifications user?s manual u16237ej3v0ud 404 ac characteristics ac test input measurement points v dd , av dd , ev dd v ss , av ss , ev ss v ih v il v ih v il measurement points ac test output measurement points ev dd ev ss v ol v oh v oh v ol measurement points load conditions dut (device under test) c l = 50 pf caution if the load capacitance exceeds 50 pf due to the circuit configuration, reduce the load capacitance of the device to 50 pf or less by in serting a buffer or by some other means.
chapter 20 electrical specifications user?s manual u16237ej3v0ud 405 clock timing (1) x1, x2 external clock input timing (t a = ? 40 to +85 c, v dd = av dd = ev dd = 2.7 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit input cycle t cyx <1> x1, x2 50 500 ns high-level width t wxh <2> x1, x2 22.5 ns low-level width t wxl <3> x1, x2 22.5 ns rise time t xr <4> 0.5 (<1> ? <2> ? <3>) ns fall time t xf <5> 0.5 (<1> ? <2> ? <3>) ns caution the duty must be within a range of 45 to 55%. x1, x2 (input) <2> <4> <5> <1> <3>
chapter 20 electrical specifications user?s manual u16237ej3v0ud 406 (2) clkout output timing (a) t a = ? 40 to +85 c, v dd = av dd = ev dd = 3.0 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf parameter symbol conditions min. max. unit output cycle t cyk <6> 0.05 31.25 s high-level width t wkh <7> 0.4<6> ? 10 ns low-level width t wkl <8> 0.4<6> ? 10 ns rise time t kr <9> 10 ns fall time t kf <10> 10 ns (b) t a = ? 40 to +85 c, v dd = av dd = ev dd = 2.7 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf parameter symbol conditions min. max. unit output cycle t cyk <6> 0.1 31.25 s high-level width t wkh <7> 0.4<6> ? 10 ns low-level width t wkl <8> 0.4<6> ? 10 ns rise time t kr <9> 10 ns fall time t kf <10> 10 ns (c) t a = ? 40 to +85 c, v dd = av dd = ev dd = 2.2 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf parameter symbol conditions min. max. unit output cycle t cyk <6> 28.57 31.25 s high-level width t wkh <7> 0.4<6> ? 15 ns low-level width t wkl <8> 0.4<6> ? 15 ns rise time t kr <9> 15 ns fall time t kf <10> 15 ns clkout (output) <7> <9> <10> <8> <6>
chapter 20 electrical specifications user?s manual u16237ej3v0ud 407 (3) pin output timing excluding pc m, pcs, pct, pdh, and pdl (a) t a = ? 40 to +85 c, v dd = av dd = ev dd = 3.0 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf parameter symbol conditions min. max. unit rise time t or <11> 20 ns fall time t of <12> 20 ns (b) t a = ? 40 to +85 c, v dd = av dd = ev dd = 2.7 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf parameter symbol conditions min. max. unit rise time t or <11> 25 ns fall time t of <12> 25 ns (c) t a = ? 40 to +85 c, v dd = av dd = ev dd = 2.2 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf parameter symbol conditions min. max. unit rise time t or <11> 30 ns fall time t of <12> 30 ns output signal <11> <12>
chapter 20 electrical specifications user?s manual u16237ej3v0ud 408 bus timing (1) read cycle (clkout asynchronous) (a) t a = ? 40 to +85 c, v dd = av dd = ev dd = 3.0 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf parameter symbol conditions min. max. unit address setup time (to rd ) t sard <13> 0.5t ? 20 ns address hold time (from rd ) t hard <14> ? 10 ns rd low-level width t wrdl <15> (1.5 + n) t ? 15 ns data setup time (to rd ) t sisd <16> 15 ns data hold time (from rd ) t hisd <17> ? 2 ns data setup time (to address) t said <18> (2 + n) t ? 30 ns t srdwt1 <19> 0.5t ? 20 ns wait setup time (to rd ) t srdwt2 <20> (0.5 + n) t ? 20 ns t hrdwt1 <21> 0.5t ns wait hold time (from rd ) t hrdwt2 <22> (0.5 + n) t ns t sawt1 <23> t ? 30 ns wait setup time (to address) t sawt2 <24> (1 + n) t ? 30 ns t hawt1 <25> t ns wait hold time (from address) t hawt2 <26> (1 + n) t ns remarks 1. t = 1/f cpu (f cpu : cpu operation clock frequency) 2. n: number of wait clocks inserted in bus cycle the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are the va lues for when clocks with a 1:1 duty ratio are input from x1.
chapter 20 electrical specifications user?s manual u16237ej3v0ud 409 (b) t a = ? 40 to +85 c, v dd = av dd = ev dd = 2.7 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf parameter symbol conditions min. max. unit address setup time (to rd ) t sard <13> 0.5t ? 25 ns address hold time (from rd ) t hard <14> ? 12 ns rd low-level width t wrdl <15> (1.5 + n) t ? 20 ns data setup time (to rd ) t sisd <16> 15 ns data hold time (from rd ) t hisd <17> ? 2 ns data setup time (to address) t said <18> (2 + n) t ? 35 ns t srdwt1 <19> 0.5t ? 25 ns wait setup time (to rd ) t srdwt2 <20> (0.5 + n) t ? 25 ns t hrdwt1 <21> 0.5t ns wait hold time (from rd ) t hrdwt2 <22> (0.5 + n) t ns t sawt1 <23> t ? 36 ns wait setup time (to address) t sawt2 <24> (1 + n) t ? 36 ns t hawt1 <25> t ns wait hold time (from address) t hawt2 <26> (1 + n) t ns remarks 1. t = 1/f cpu (f cpu : cpu operation clock frequency) 2. n: number of wait clocks inserted in bus cycle the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are the va lues for when clocks with a 1:1 duty ratio are input from x1.
chapter 20 electrical specifications user?s manual u16237ej3v0ud 410 (2) write cycle (clkout asynchronous) (a) t a = ? 40 to +85 c, v dd = av dd = ev dd = 3.0 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf parameter symbol conditions min. max. unit address setup time (to wrm ) t saw <27> t ? 20 ns address hold time (from wrm ) t haw <28> 0.5t ? 15 ns wrm low-level width t wwrl <29> (0.5 + n) t ? 15 ns data output time from wrm t dosdw <30> ? 7 ns data setup time (to wrm ) t sosdw <31> (0.5 + n) t ? 15 ns data hold time (from wrm ) t hosdw <32> 0.5t ? 15 ns data setup time (to address) t saod <33> t ? 25 ns t swrwt1 <34> 20 ns wait setup time (to wrm ) t swrwt2 <35> nt ? 20 ns t hwrwt1 <36> 0 ns wait hold time (from wrm ) t hwrwt2 <37> nt ns t sawt1 <38> t ? 30 ns wait setup time (to address) t sawt2 <39> (1 + n) t ? 30 ns t hawt1 <40> t ns wait hold time (from address) t hawt2 <41> (1 + n) t ns remarks 1. m = 0, 1 2. t = 1/f cpu (f cpu : cpu operation clock frequency) 3. n: number of wait clocks inserted in bus cycle the sampling timing changes when a programmable wait is inserted. 4. the values in the above specifications are the va lues for when clocks with a 1:1 duty ratio are input from x1.
chapter 20 electrical specifications user?s manual u16237ej3v0ud 411 (b) t a = ? 40 to +85 c, v dd = av dd = ev dd = 2.7 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf parameter symbol conditions min. max. unit address setup time (to wrm ) t saw <27> t ? 25 ns address hold time (from wrm ) t haw <28> 0.5t ? 20 ns wrm low-level width t wwrl <29> (0.5 + n) t ? 20 ns data output time from wrm t dosdw <30> ? 9 ns data setup time (to wrm ) t sosdw <31> (0.5 + n) t ? 20 ns data hold time (from wrm ) t hosdw <32> 0.5t ? 20 ns data setup time (to address) t saod <33> t ? 25 ns t swrwt1 <34> 22 ns wait setup time (to wrm ) t swrwt2 <35> nt ? 22 ns t hwrwt1 <36> 0 ns wait hold time (from wrm ) t hwrwt2 <37> nt ns t sawt1 <38> t ? 36 ns wait setup time (to address) t sawt2 <39> (1 + n) t ? 36 ns t hawt1 <40> t ns wait hold time (from address) t hawt2 <41> (1 + n) t ns remarks 1. m = 0, 1 2. t = 1/f cpu (f cpu : cpu operation clock frequency) 3. n: number of wait clocks inserted in bus cycle the sampling timing changes when a programmable wait is inserted. 4. the values in the above specifications are the va lues for when clocks with a 1:1 duty ratio are input from x1.
chapter 20 electrical specifications user?s manual u16237ej3v0ud 412 read cycle (clkout asynchronous, 1 wait) clkout (output) t1 <18> hi-z hi-z <13> <15> <22> <20> <21> <19> <23> <25> <24> <26> <17> <16> <14> tw t2 rd (output) cs0 to cs2 (output) a0 to a18 (output) d0 to d15 (i/o) wait (input)
chapter 20 electrical specifications user?s manual u16237ej3v0ud 413 write cycle (clkout asynchronous, 1 wait) clkout (output) t1 <33> <27> <30> <29> <37> <35> <36> <34> <38> <40> <39> <41> <32> <31> <28> tw t2 wr0, wr1 (output) cs0 to cs2 (output) a0 to a18 (output) d0 to d15 (i/o) wait (input) hi-z hi-z
chapter 20 electrical specifications user?s manual u16237ej3v0ud 414 reset/interrupt timing (a) t a = ? 40 to +85c, v dd = av dd = ev dd = 2.7 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf parameter symbol conditions min. max. unit reset high-level width t wrsh <42> 500 ns reset low-level width t wrsl <43> 500 ns nmi high-level width t wnih <44> 500 ns nmi low-level width t wnil <45> 500 ns intpn high-level width t withn <46> n = 0 to 2 500 ns intpn low-level width t witln <47> n = 0 to 2 500 ns remark t = 1/f xx (b) t a = ? 40 to +85c, v dd = av dd = ev dd = 2.2 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf parameter symbol conditions min. max. unit reset high-level width note t wrsh <42> 600 ns reset low-level width note t wrsl <43> 600 ns nmi high-level width t wnih <44> 600 ns nmi low-level width t wnil <45> 600 ns intpn high-level width t withn <46> n = 0 to 2 600 ns intpn low-level width t witln <47> n = 0 to 2 600 ns note release reset when v dd is 2.7 v or higher. remark t = 1/f xx
chapter 20 electrical specifications user?s manual u16237ej3v0ud 415 reset reset (input) <42> <43> interrupt nmi (input) intpn (input) <44> <45> <46> <47> remark n = 0 to 2
chapter 20 electrical specifications user?s manual u16237ej3v0ud 416 timer timing (a) t a = ? 40 to +85c, v dd = av dd = ev dd = 2.7 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf parameter symbol conditions min. max. unit tin high-level width t wtihn n = 0m0, 0m1 note , 10, 11, 20, 21 2t + 20 ns tin low-level width t wtiln n = 0m0, 0m1 note , 10, 11, 20, 21 2t + 20 ns tclrm high-level width t wtchm m = 10, 11 2t + 20 ns tclrm low-level width t wtclm m = 10, 11 2t + 20 ns intpm high-level width t withm m = 100, 101, 110, 111 2t + 20 ns intpm low-level width t witlm m = 100, 101, 110, 111 2t + 20 ns note t is equal to one cycle of the tm0m (m = 0 to 3) coun t clock when ti0m0 or ti0m1 (m = 0 to 3) is input as the capture trigger. it is 1/f xx when ti0m0 or ti0m1 is i nput as the external clock. remark t = 1/f xx
chapter 20 electrical specifications user?s manual u16237ej3v0ud 417 csi timing (1) master mode (t a = ? 40 to +85c, v dd = av dd = ev dd = 2.7 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit ev dd = 3.0 to 3.6 v 200 ns sckn cycle time t kcyn <48> ev dd = 2.7 to 3.6 v 400 ns ev dd = 3.0 to 3.6 v t kcyn /2 ? 20 ns sckn high-/low-level width t khn , t kln <49> ev dd = 2.7 to 3.6 v t kcyn /2 ? 25 ns ev dd = 3.0 to 3.6 v 30 ns sin setup time (to sckn ) t sikn <50> ev dd = 2.7 to 3.6 v 30 ns ev dd = 3.0 to 3.6 v 30 ns sin setup time (to sckn ) t sikn <50> ev dd = 2.7 to 3.6 v 30 ns ev dd = 3.0 to 3.6 v 30 ns sin hold time (from sckn ) t ksin <51> ev dd = 2.7 to 3.6 v 30 ns ev dd = 3.0 to 3.6 v 30 ns sin hold time (from sckn ) t ksin <51> ev dd = 2.7 to 3.6 v 30 ns ev dd = 3.0 to 3.6 v 30 ns delay time from sckn to son output t kson <52> ev dd = 2.7 to 3.6 v 30 ns ev dd = 3.0 to 3.6 v 30 ns delay time from sckn to son output t kson <52> ev dd = 2.7 to 3.6 v 30 ns ev dd = 3.0 to 3.6 v t kcyn /2 ? 20 ns hold time from sckn to son output t hskson <53> ev dd = 2.7 to 3.6 v t kcyn /2 ? 25 ns ev dd = 3.0 to 3.6 v t kcyn /2 ? 20 ns hold time from sckn to son output t hskson <53> ev dd = 2.7 to 3.6 v t kcyn /2 ? 25 ns remark n = 0, 1
chapter 20 electrical specifications user?s manual u16237ej3v0ud 418 (2) slave mode (t a = ? 40 to +85c, v dd = av dd = ev dd = 2.7 to 3.6 v, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit ev dd = 3.0 to 3.6 v 200 ns sckn cycle time t kcyn <48> ev dd = 2.7 to 3.6 v 400 ns ev dd = 3.0 to 3.6 v 90 ns sckn high-/low-level width t khn , t kln <49> ev dd = 2.7 to 3.6 v 190 ns ev dd = 3.0 to 3.6 v 50 ns sin setup time (to sckn ) t sikn <50> ev dd = 2.7 to 3.6 v 50 ns ev dd = 3.0 to 3.6 v 50 ns sin setup time (to sckn ) t sikn <50> ev dd = 2.7 to 3.6 v 50 ns ev dd = 3.0 to 3.6 v 50 ns sin hold time (from sckn ) t ksin <51> ev dd = 2.7 to 3.6 v 50 ns ev dd = 3.0 to 3.6 v 50 ns sin hold time (from sckn ) t ksin <51> ev dd = 2.7 to 3.6 v 50 ns ev dd = 3.0 to 3.6 v 50 ns delay time from sckn to son output t kson <52> ev dd = 2.7 to 3.6 v 50 ns ev dd = 3.0 to 3.6 v 50 ns delay time from sckn to son output t kson <52> ev dd = 2.7 to 3.6 v 50 ns ev dd = 3.0 to 3.6 v t khn ns hold time from sckn to son output t hskson <53> ev dd = 2.7 to 3.6 v t khn ns ev dd = 3.0 to 3.6 v t kln ns hold time from sckn to son output t hskson <53> ev dd = 2.7 to 3.6 v t kln ns remark n = 0, 1
chapter 20 electrical specifications user?s manual u16237ej3v0ud 419 (3) timing when csicn.ckpn and csicn.dapn bits = 00 <48> <49> <49> <50> <51> <52> <53> sin (input) son (output) sckn (i/o) input data output data remarks 1. broken lines indicate high impedance. 2. n = 0, 1 (4) timing when csicn.ckpn and csicn.dapn bits = 01 <50> <51> <53> sin (input) son (output) input data output data <48> <49> <49> sckn (i/o) <52> remarks 1. broken lines indicate high impedance. 2. n = 0, 1
chapter 20 electrical specifications user?s manual u16237ej3v0ud 420 (5) timing when csicn.ckpn and csicn.dapn bits = 10 <48> <49> <49> <50> <51> <52> <53> sin (input) son (output) sckn (i/o) input data output data remarks 1. broken lines indicate high impedance. 2. n = 0, 1 (6) timing when csicn.ckpn and csicn.dapn bits = 11 <50> <51> <53> sin (input) son (output) input data output data <48> <49> <49> sckn (i/o) <52> remarks 1. broken lines indicate high impedance. 2. n = 0, 1
chapter 20 electrical specifications user?s manual u16237ej3v0ud 421 a/d converter characteristics (1) recommended ope rating conditions (t a = ? 40 to +85 c, v ss = av ss = ev ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit av dd 3.0 3.3 3.6 v ev dd 3.0 3.3 3.6 v supply voltage v dd 3.0 3.3 3.6 v clock frequency f xx 20 mhz operating ambient temperature t a ? 40 27 +85 c (2) reference (under recomm ended operating conditions) parameter symbol conditions min. typ. max. unit external reference potential (input) av refin 1.2 1.25 v internal reference potential (output) av refout ? 5.0% 1.226 +5.0% v internal reference potential temperature coefficient note 52 ppm/ c reference smoothing capacitance c ref 10 f note temperature coefficient of ? 40 c to +25 c and +25 c to +100 c (3) analog input specifications parameter symbol conditions min. typ. max. unit voltage ch ? 20 0 +20 mv gain: 2 ? 10 0 +10 mv input signal dc level current ch gain: 16 ? 1.25 0 +1.25 mv voltage ch ? 0.375 +0.375 v gain: 2 ? 0.1875 +0.1875 v input signal range current ch gain: 16 ? 23.4 +23.4 mv voltage ch ? 7% 1 +7% ? gain: 2 ? 7% 2 +7% ? input gain note current ch gain: 16 ? 7% 16 +7% ? voltage ch 100 125 k ? gain: 2 60 75 k ? input impedance current ch gain: 16 60 75 k ? note the gain of all the current chs is 16 if the 16 gain mode is selected for even one current ch. remarks 1. n = 0 to 5 2. voltage ch: channels 0, 2, and 4 current ch: channels 1, 3, and 5
chapter 20 electrical specifications user?s manual u16237ej3v0ud 422 (4) a/d converter and system specifications parameter symbol conditions min. typ. max. unit a/d converter and system (fs = 4340 hz) system clock f xx 20 mhz ? operation clock dsclk f xx /12 1.667 mhz oversampling frequency fos dsclk/3 555.6 khz sampling frequency fs fos/128 4.34 khz data width 16 bit voltage ch 70 76 db current ch, gain: 2 70 76 db s/n snr 0 db, 60 hz single sine wave input current ch, gain: 16 62 69 db voltage ch ? 80 ? 72 db current ch, gain: 2 ? 80 ? 72 db thd thd 0 db, 60 hz single sine wave input current ch, gain: 16 ? 80 ? 72 db inter-channel isolation xt 80 db operating current iav dd 4.6 10.0 ma startup operating current isav dd only at startup time 15 30 ma startup time t stup r = 43 k ? , c = 0.22 f 20 ms a/d converter and system (fs = 2170 hz) system clock f xx 20 mhz ? operation clock dsclk f xx /24 0.833 mhz oversampling frequency fos dsclk/3 277.8 khz sampling frequency fs fos/128 2.17 khz data width 16 bit voltage ch 70 76 db current ch, gain: 2 70 76 db s/n snr 0 db, 60 hz single sine wave input current ch, gain: 16 62 69 db voltage ch ? 80 ? 72 db current ch, gain: 2 ? 80 ? 72 db thd thd 0 db, 60 hz single sine wave input current ch, gain: 16 ? 80 ? 72 db inter-channel isolation xt 80 db operating current iav dd 4.6 10.0 ma startup operating current isav dd only at startup time 15 30 ma startup time t stup r = 43 k ? , c = 0.22 f 20 ms remarks 1. voltage ch: channels 0, 2, and 4 current ch: channels 1, 3, and 5 2. s/n: ratio of the signal frequency component to the sum of the paramet ers other than the signal frequency and harmonic component when a signal (0 db, 60 hz) is input 3. thd: sum of the harmonic component when a signal (0 db, 60 hz) is input 4. startup time (t stup ): time since the a/d converter power supply is switched on and until the operating current reaches to a value less than the maximum value (iav dd ) (c is a capacitance to stabilize av refin and r is a limiting resistance).
chapter 20 electrical specifications user?s manual u16237ej3v0ud 423 (5) digital filter specifications parameter symbol conditions min. typ. max. unit digital filter characteristics (fs = 4340 hz) pass region (low region) fchpf ? 3 db 0.73 hz in-band ripple 1 rp1 50 hz at center, 45 hz to 55 hz 60 hz at center, 54 hz to 66 hz ? 0.01 +0.01 db in-band ripple 2 rp2 50 hz at center, 45 hz to 275 hz 60 hz at center, 54 hz to 330 hz ? 0.1 +0.1 db in-band ripple 3 rp3 50 hz at center, 45 hz to 1,100 hz 60 hz at center, 54 hz to 1,320 hz ? 0.1 +0.1 db block region (high region) fatt ? 80 db 3020 hz attenuation out of band att ? 80 db digital filter characteristics (fs = 2170 hz) pass region (low region) fchpf ? 3 db 0.365 hz in-band ripple 1 rp1 50 hz at center, 45 hz to 55 hz 60 hz at center, 54 hz to 66 hz ? 0.01 +0.01 db in-band ripple 2 rp2 50 hz at center, 45 hz to 275 hz 60 hz at center, 54 hz to 330 hz ? 0.1 +0.1 db block region (high region) fatt ? 80 db 1,510 hz attenuation out of band att ? 80 db
user?s manual u16237ej3v0ud 424 chapter 21 package drawing 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 ? 0.04 m 0.17 + 0.03 ? 0.07 r3 + 7 ? 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h
user?s manual u16237ej3v0ud 425 chapter 22 recommended soldering conditions the v850es/pm1 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for details of the recommended soldering conditions, see the semiconductor device mount manual website (http://www.necel.com/pkg/en/mount/index.html). table 22-1. surface mounting type solderi ng conditions (1) pd703228gc-003-8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703228gc- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 30 seconds max. (at 210c or higher), count: three times or less, exposure limit: 3 days note (after that, prebake at 125c for 36 to 72 hours) ir60-363-3 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). (2) pd703228gc-004-8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) pd703228gc- -8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125c for 20 to 72 hours) ir60-207-3 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). remark products with -a at the end of the part number are lead-free products.
user?s manual u16237ej3v0ud 426 appendix a register index (1/6) symbol name unit page adcr0 a/d conversion result register 0 adc 285 adcr1 a/d conversion result register 1 adc 285 adcr2 a/d conversion result register 2 adc 285 adcr3 a/d conversion result register 3 adc 285 adcr4 a/d conversion result register 4 adc 285 adcr5 a/d conversion result register 5 adc 285 adic interrupt control register intc 353 adly a/d clock delay setting register adc 285 adm a/d converter mode register adc 284 asif0 asynchronous serial interface transmit status register 0 uart 303 asif1 asynchronous serial interface transmit status register 1 uart 303 asim0 asynchronous serial interface mode register 0 uart 299 asim1 asynchronous serial interface mode register 1 uart 299 asis0 asynchronous serial interface status register 0 uart 302 asis1 asynchronous serial interface status register 1 uart 302 awc address wait control register bcu 134 bcc bus cycle control register bcu 135 brgc0 baud rate generator control register 0 uart 321 brgc1 baud rate generator control register 1 uart 321 bsc bus size configuration register bcu 124 cc100 16-bit timer capture/compare register 100 tm1 220 cc101 16-bit timer capture/compare register 101 tm1 220 cc110 16-bit timer capture/compare register 110 tm1 220 cc111 16-bit timer capture/compare register 111 tm1 220 ccic100 interrupt control register intc 353 ccic101 interrupt control register intc 353 ccic110 interrupt control register intc 353 ccic111 interrupt control register intc 353 cksr0 clock select register 0 uart 320 cksr1 clock select register 1 uart 320 corad0 correction address register 0 romc 392 corad0h correction address register 0h romc 392 corad0l correction address register 0l romc 392 corad1 correction address register 1 romc 392 corad1h correction address register 1h romc 392 corad1l correction address register 1l romc 392 corad2 correction address register 2 romc 392 corad2h correction address register 2h romc 392 corad2l correction address register 2l romc 392
appendix a register index user?s manual u16237ej3v0ud 427 (2/6) symbol name unit page corad3 correction address register 3 romc 392 corad3h correction address register 3h romc 392 corad3l correction address register 3l romc 392 corcn correction control register romc 393 cr000 16-bit timer capture/compare register 000 tm0 149 cr001 16-bit timer capture/compare register 001 tm0 150 cr010 16-bit timer capture/compare register 010 tm0 149 cr011 16-bit timer capture/compare register 011 tm0 150 cr020 16-bit timer capture/compare register 020 tm0 149 cr021 16-bit timer capture/compare register 021 tm0 150 cr030 16-bit timer capture/compare register 030 tm0 149 cr031 16-bit timer capture/compare register 031 tm0 150 cr2 16-bit timer compare register 2 tm2 247 cr20 8-bit timer compare register 20 tm2 247 cr21 8-bit timer compare register 21 tm2 247 crc00 capture/compare control register 00 tm0 155 crc01 capture/compare control register 01 tm0 155 crc02 capture/compare control register 02 tm0 155 crc03 capture/compare control register 03 tm0 155 csic0 clocked serial interface clock select register 0 csi 330 csic1 clocked serial interface clock select register 1 csi 330 csiic0 interrupt control register intc 353 csiic1 interrupt control register intc 353 csim0 clocked serial interf ace mode register 0 csi 329 csim1 clocked serial interf ace mode register 1 csi 329 day day count register rtc 269 dayb day count setting register rtc 269 dwc0 data wait control register 0 bcu 132 hour hour count register rtc 268 hourb hour count setting register rtc 269 hourday day/hour count register rtc 53 hourdayb day/hour count setting register rtc 53 hpfc0 high-pass filter control register 0 adc 285 imr0 interrupt mask register 0 intc 354 imr0h interrupt mask register 0h intc 354 imr0l interrupt mask register 0l intc 354 imr1 interrupt mask register 1 intc 354 imr1h interrupt mask register 1h intc 354 imr1l interrupt mask register 1l intc 354 intf0 external interrupt falling edge specification register 0 intc 358 intr0 external interrupt rising edge specification register 0 intc 358 ispr in-service priority register intc 355 min minute count register rtc 268 minb minute count setting register rtc 268
appendix a register index user?s manual u16237ej3v0ud 428 (3/6) symbol name unit page osts oscillation stabilization time select register standby 372 ovfic10 interrupt control register intc 353 ovfic11 interrupt control register intc 353 p0 port 0 port 68 p1 port 1 port 71 p2 port 2 port 74 p3 port 3 port 76 p4 port 4 port 79 p9 port 9 port 83 p9h port 9h port 83 p9l port 9l port 83 pcc processor clock control register cg 143 pcm port cm port 87 pcs port cs port 89 pct port ct port 91 pdh port dh port 93 pdl port dl port 96 pdlh port dlh port 96 pdll port dll port 96 pfc0 port 0 function control register port 69 pfc1 port 1 function control register port 73 pfc3 port 3 function control register port 78 pfc4 port 4 function control register port 81 pfc9 port 9 function control register port 86 pfc9h port 9 function control register h port 86 pfc9l port 9 function control register l port 86 pic0 interrupt control register intc 353 pic1 interrupt control register intc 353 pic2 interrupt control register intc 353 pm0 port 0 mode register port 68 pm1 port 1 mode register port 71 pm2 port 2 mode register port 74 pm3 port 3 mode register port 76 pm4 port 4 mode register port 79 pm9 port 9 mode register port 83 pm9h port 9 mode register h port 83 pm9l port 9 mode register l port 83 pmc0 port 0 mode control register port 69 pmc1 port 1 mode control register port 72 pmc2 port 2 mode control register port 75 pmc3 port 3 mode control register port 77 pmc4 port 4 mode control register port 80 pmc9 port 9 mode control register port 84 pmc9h port 9 mode control register h port 84
appendix a register index user?s manual u16237ej3v0ud 429 (4/6) symbol name unit page pmc9l port 9 mode control register l port 84 pmccm port cm mode control register port 88 pmccs port cs mode control register port 90 pmcct port ct mode control register port 92 pmcdh port dh mode control register port 94 pmcdl port dl mode control register port 97 pmcdlh port dl mode control register h port 97 pmcdll port dl mode control register l port 97 pmcm port cm mode register port 87 pmcs port cs mode register port 89 pmct port ct mode register port 91 pmdh port dh mode register port 93 pmdl port dl mode register port 96 pmdlh port dl mode register h port 96 pmdll port dl mode register l port 96 prcmd command register cpu 57 prm00 prescaler mode register 00 tm0 158 prm01 prescaler mode register 01 tm0 158 prm02 prescaler mode register 02 tm0 158 prm03 prescaler mode register 03 tm0 158 psc power save control register standby 371 psmr power save mode register standby 371 pu0 pull-up resistor option register 0 port 70 pu1 pull-up resistor option register 1 port 73 pu2 pull-up resistor option register 2 port 75 pu3 pull-up resistor option register 3 port 78 pu4 pull-up resistor option register 4 port 81 pwmb0 pwm buffer register 0 pwm 291 pwmb1 pwm buffer register 1 pwm 291 pwmb2 pwm buffer register 2 pwm 291 pwmb3 pwm buffer register 3 pwm 291 pwmc0 pwm control register 0 pwm 290 pwmc1 pwm control register 1 pwm 290 pwmc2 pwm control register 2 pwm 290 pwmc3 pwm control register 3 pwm 290 rovic interrupt control register intc 353 rtcc rtc control register rtc 52 rtcc0 rtc control register 0 rtc 265 rtcc1 rtc control register 1 rtc 266 rtcic interrupt control register intc 353 rxb0 receive buffer register 0 uart 304 rxb1 receive buffer register 1 uart 304 sec second count register rtc 267 secb second count setting register rtc 267
appendix a register index user?s manual u16237ej3v0ud 430 (5/6) symbol name unit page secmin minute/second count register rtc 52 secminb minute/second count setting register rtc 53 ses10 valid edge select register 10 tm1 226 ses11 valid edge select register 11 tm1 226 sio0 serial i/o shift register 0 csi 331 sio1 serial i/o shift register 1 csi 331 sioe0 receive-only serial i/o shift register 0 csi 332 sioe1 receive-only serial i/o shift register 1 csi 332 sotb0 clocked serial interface transmit buffer register 0 csi 332 sotb1 clocked serial interface transmit buffer register 1 csi 332 sreic0 interrupt control register intc 353 sreic1 interrupt control register intc 353 sric0 interrupt control register intc 353 sric1 interrupt control register intc 353 stic0 interrupt control register intc 353 stic1 interrupt control register intc 353 subc sub-count register rtc 267 subch sub-count register h rtc 52 subcl sub-count register l rtc 52 sys system status register cpu 58 tcl2 timer clock select register 2 tm2 52 tcl20 timer clock selection register 20 tm2 248 tcl21 timer clock selection register 21 tm2 248 tm00 16-bit timer counter 00 tm0 149 tm01 16-bit timer counter 01 tm0 149 tm02 16-bit timer counter 02 tm0 149 tm03 16-bit timer counter 03 tm0 149 tm10 16-bit timer counter 10 tm1 218 tm11 16-bit timer counter 11 tm1 218 tm2 16-bit timer counter 2 tm2 52 tm20 8-bit timer counter 20 tm2 246 tm21 8-bit timer counter 21 tm2 246 tmc00 16-bit timer mode control register 00 tm0 153 tmc01 16-bit timer mode control register 01 tm0 153 tmc02 16-bit timer mode control register 02 tm0 153 tmc03 16-bit timer mode control register 03 tm0 153 tmc100 16-bit timer mode control register 100 tm1 222 tmc101 16-bit timer mode control register 101 tm1 224 tmc110 16-bit timer mode control register 110 tm1 222 tmc111 16-bit timer mode control register 111 tm1 224 tmc2 16-bit timer mode control register 2 tm2 52 tmc20 8-bit timer mode control register 20 tm2 249 tmc21 8-bit timer mode control register 21 tm2 249
appendix a register index user?s manual u16237ej3v0ud 431 (6/6) symbol name unit page tmic000 interrupt control register intc 353 tmic001 interrupt control register intc 353 tmic010 interrupt control register intc 353 tmic011 interrupt control register intc 353 tmic020 interrupt control register intc 353 tmic021 interrupt control register intc 353 tmic030 interrupt control register intc 353 tmic031 interrupt control register intc 353 tmic20 interrupt control register intc 353 tmic21 interrupt control register intc 353 toc00 16-bit timer output control register 00 tm0 156 toc01 16-bit timer output control register 01 tm0 156 toc02 16-bit timer output control register 02 tm0 156 toc03 16-bit timer output control register 03 tm0 156 txb0 transmit buffer register 0 uart 305 txb1 transmit buffer register 1 uart 305 vswc system wait control register bcu 59 wdcs watchdog timer clock select register wdt 275 wdres wdt reset status register cg 279 wdtic interrupt control register intc 353 wdtm watchdog timer mode register wdt 276 week week count register rtc 270 weekb week count setting register rtc 270 weekbh week count setting register h rtc 53 weekbl week count setting register l rtc 53 weekh week count register h rtc 53 weekl week count register l rtc 53
user?s manual u16237ej3v0ud 432 appendix b instruction set list b.1 conventions (1) symbols used to describe operands symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used main ly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the remainders of division result s and the higher 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the condition codes sp stack pointer (r3) ep element pointer (r30) listx x item register list (2) symbols used to describe opcodes symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list
appendix b instruction set list user?s manual u16237ej3v0ud 433 (3) symbols used in operations symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) half-word halfword (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) symbols used in execution clock symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency).
appendix b instruction set list user?s manual u16237ej3v0ud 434 (5) symbols used in flag operations symbol explanation (blank) no change 0 clear to 0 set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition name (cond) condition code (cccc) condition formula explanation v 0 0 0 0 ov = 1 overflow nv 1 0 0 0 ov = 0 no overflow c/l 0 0 0 1 cy = 1 carry lower (less than) nc/nl 1 0 0 1 cy = 0 no carry not lower (greater than or equal) z 0 0 1 0 z = 1 zero nz 1 0 1 0 z = 0 not zero nh 0 0 1 1 (cy or z) = 1 not higher (less than or equal) h 1 0 1 1 (cy or z) = 0 higher (greater than) s/n 0 1 0 0 s = 1 negative ns/p 1 1 0 0 s = 0 positive t 0 1 0 1 ? always (unconditional) sa 1 1 0 1 sat = 1 saturated lt 0 1 1 0 (s xor ov) = 1 less than signed ge 1 1 1 0 (s xor ov) = 0 greater than or equal signed le 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed gt 1 1 1 1 ((s xor ov) or z) = 0 greater than signed
appendix b instruction set list user?s manual u16237ej3v0ud 435 b.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 r r r r r 0 1 0 010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 when conditions are satisfied 2 note 2 2 note 2 2 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 1 1 1 bsh reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23 : 16) ll gr[reg2] (31 : 24) ll gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) 1 1 1 0 bsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) ll gr [reg2] (23 : 16) ll gr[reg2] (31 : 24) 1 1 1 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,half-word)) 4 4 4 bit#3, disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 r r r r r 1 1 1 111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extend(imm5) else gr[reg3] gr[reg2] 1 1 1 cmov cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 r r r r r wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1,reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 r r r r r 0 1 0 011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 3 3 3 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 3 3 3 r r r r r
appendix b instruction set list user?s manual u16237ej3v0ud 436 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2 (returned pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 3 3 3 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12[reg1] 0000011001iiiiil lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2](15 : 0) ll gr[reg2] (31 : 16) 1 1 1 0 jarl disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 2 2 2 jmp [reg1] 00000000011rrrrr pc gr[reg1] 3 3 3 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 2 2 2 ld.b disp16[reg1],reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 11 ld.bu disp16[reg1],reg2 r r rr r1 11 10 b rrrrr ddddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 11
appendix b instruction set list user?s manual u16237ej3v0ud 437 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,half-word)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 r r rr r1 11 11 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,half-word) 1 1 note 11 ld.w disp16[reg1],reg2 r r rr r1 11 00 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] load-memory(adr,word) 1 1 note 11 reg1,reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 r r r r r 0 1 0 000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mul imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 1 4 5 reg1,reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 1 1 2 mulh imm5,reg2 r r r r r 0 1 0 111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 1 1 2 mulhi imm16,reg1,reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 1 1 2 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mulu imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 1 4 5 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 r r rr r0 00 00 1 rrrrr gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3
appendix b instruction set list user?s manual u16237ej3v0ud 438 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory(sp?4,gr[reg in list12],word) sp sp ? 4 repeat 1 step above until all regs in list12 is stored sp sp ? zero-extend (imm5) ep sp/imm n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 3 3 3 r r r r r reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend (imm5) 1 1 1 0 sasf cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 1 1 1 reg1,reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5)) 1 1 1 satsub reg1,reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16)) 1 1 1 satsubr reg1,reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1
appendix b instruction set list user?s manual u16237ej3v0ud 439 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 1 1 1 0 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 1 1 1 0 sld.b disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 18 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 9 sld.h disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,half-word)) 1 1 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,half- word)) 1 1 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 1 1 note 9 sst.b reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 1 1 1 sst.h reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],half-word) 1 1 1 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 1 1 1 st.b reg2,disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 1 1 1 st.h reg2,disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], half-word) 1 1 1 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], word) 1 1 1 stsr regid,reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1
appendix b instruction set list user?s manual u16237ej3v0ud 440 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr[reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory (adr,half-word))) logically shift left by 1 5 5 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend(gr[reg1] (7 : 0)) 1 1 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend(gr[reg1] (15 : 0)) 1 1 1 trap vector 00000111111iiiii 0000000100000000 eipc pc+4 (return pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh) 00000050h (when vector is 10h to 1fh) 3 3 3 tst reg1,reg2 r r rr r0 01 01 1 rrrrr result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit (adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7 : 0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15 : 0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 3 if there is an instruction that rewrites the contents of the psw immediately before. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (a ccording to the number of wait states. also, if there are no wait states, n is the num ber of list12 registers. if n = 0, same operation as when n = 1) 5. rrrrr: other than 00000. 6. the lower halfword data only are valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states).
appendix b instruction set list user?s manual u16237ej3v0ud 441 notes 12. in this instruction, for convenience of mnemonic descr iption, the source register is made reg2, but the reg1 field is used in the opcode. therefore, the m eaning of register specific ation in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. do not specify the same register fo r general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other than 00 000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8.
user?s manual u16237ej3v0ud 442 appendix c revision history c.1 major revisions in this edition page description p. 15 addition of part number to 1.4 ordering information p. 34 modification of note in table 3-2 system register numbers p. 38 addition of description to 3.2.2 (6) exception/debug trap status saving registers (dbpc and dbpsw) p. 40 addition of caution to 3.3.2 specifying operation mode pp. 49, 51 modification of default value in 3.4.6 peripheral i/o registers p. 62 addition of 3.4.8 (3) restriction on conflict between sld instruction and interrupt request p. 84 modification of 4.3.6 (1) (c) port 9 mode control register (pmc9) p. 147 modification of style in chapter 7 16-bit timer/event counters 00 to 03 p. 282 addition of figure 12-2 example of recommended external connection of av refin /av refout pin p. 422 addition of startup operating current, startup time, and remark 4 to (4) a/d converter and system specifications in a/d converter characteristics p. 425 addition of (2) to table 22-1 surface mounting type soldering conditions
appendix c revision history user?s manual u16237ej3v0ud 443 c.2 revision history of preceding editions (1/2) edition description chapter modification of table 2-2 operating status of each pin in each operation mode modification of i/o circuit type of p98 to p915 in 2.3 types of pin i/o circuits, i/o buffer power supplies, and connection of unused pins modification of figure 2-1 pin i/o circuits chapter 2 pin functions addition of 3.4.8 (2) access to special on-chip peripheral i/o registers chapter 3 cpu function addition of 4.4 block diagram addition of 4.6 cautions chapter 4 port functions modification of 5.2.1 pin status when internal rom, internal ram, or on-chip peripheral i/o is accessed addition of caution to 5.5.4 (1) address wait control register (awc) chapter 5 bus control function addition of caution 3 to 6.3 (1) processor clock control register (pcc) modification of 6.3 (1) (a) example of setting main clock operation subclock operation modification of 6.3 (1) (b) example of setting subclock operation main clock operation addition of 6.4.3 external clock input function chapter 6 clock generation function addition of caution 2 to 7.2 (3) 16-bit timer capture/compare register 0n1 (cr0n1) modification of caution 3 in 7.3 (2) capture/compare control register 0n (crc0n) addition of caution 6 to 7.3 (3) 16-bit timer output control register 0n (toc0n) addition of setting method to 7.4.1 operation as interval timer (16 bits) modification of figure 7-4 timing of interval timer operation addition of setting method to 7.4.2 ppg output operation addition of figure 7-6 configuration of ppg output addition of figure 7-7 ppg output operation timing addition of setting method to 7.4.3 pulse width measurement addition of setting method to 7.4.4 operation as external event counter addition of setting method to 7.4.5 square-wave output operation addition of setting method to 7.4.6 one-shot pulse output operation addition of <2> to 7.4.7 (3) data hold timing of capture register modification of (b) in 7.4.7 (8) capture operation chapter 7 16-bit timer/event counters 00 to 03 addition of caution 3 to 8.3 (1) 16-bit timer counters 10 and 11 (tm10 and tm11) addition of caution to 8.3 (2) 16-bit timer capture/compare registers 1n0 and 1n1 (cc1n0 and cc1n1) addition of caution 3 to 8.4 (1) 16-bit timer mode control registers 100 and 110 (tmc100 and tmc110) addition of note to 8.6 (4) cycle measurement chapter 8 16-bit timer/event counters 10 and 11 addition of caution to 11.3 (2) watchdog timer mode register (wdtm) chapter 11 watchdog timer functions addition of (7) to 12.5 cautions chapter 12 a/d converter addition of caution to 13.3 (2) pwm buffer register n (pwmbn) modification of figure 13-2 pwmn operation timing 2nd modification of figure 13-3 operation timing when pwmbn register is set to 00h/ffh chapter 13 pwm function
appendix c revision history user?s manual u16237ej3v0ud 444 (2/2) edition description chapter addition of caution 2 to 14.3 (1) asynchronous serial interface mode register n (asimn) addition of caution 2 to 14.3 (2) asynchronous serial interface status register n (asisn) addition of caution to 14.5 (3) continuous transmission operation modification of figure 14-7 asynchronous serial interface reception completion interrupt timing chapter 14 asynchronous serial interface n (uartn) addition of note to 17.2 (1) power save control register (psc) addition of caution 2 to 17.3.1 setting and operation status modification of note in table 17-3 operation status in halt mode addition of 17.7.3 registers to which access is disabled in subclock operation mode addition of note to table 17-8 operation status in subclock operation mode chapter 17 standby function addition of note 2 and modification of note 3 in table 18-1 hardware status on reset pin input chapter 18 reset function modification of figure 19-2 rom correction operation and program flow chapter 19 rom correction function addition of oscillation frequency to recommended oscillator (2) external clock input modification of description of oscillation stabilization time in recommended oscillator (3) subclock oscillator modification of conditions of power supply voltage in dc characteristics 1 (a) modification of dc characteristics 1 (b) modification of conditions of power supply voltage in dc characteristics 2 modification of i dd1 and addition of note 2 to i dd3 in dc characteristics 2 addition of note 3 to i dd4 , i dd5 , and i dd6 in dc characteristics 2 addition of note 1 to i dddr in data retention characteristics modification of t cyx , t wxh , and t wxl of (1) , and t cyk , t wkh , and t wkl of (2) (a) , addition of (2) (b) , modification of (2) (c) and (3) (b) , and addition of (3) (c) in clock timing modification of (1) (b) and (2) (b) in bus timing modification of conditions of power supply voltage in reset/interrupt timing (a) modification of reset/interrupt timing (b) modification of conditions of power supply voltage in timer timing (a) modification of csi timing modification of internal reference potent ial temperature coefficient and addition of note in (2) reference in a/d converter characteristics modification of s/n and operating current and addition of remarks 2 and 3 in (4) a/d converter and system specifications in a/d converter characteristics chapter 20 electrical specifications addition of chapter 22 recommended soldering conditions chapter 22 recommended soldering conditions 2nd addition of appendix c revision history appendix c revision history
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